From c275d64712c1aee8d81f6b6505333f577d075bf6 Mon Sep 17 00:00:00 2001
From: Schuyler Eldridge
Date: Fri, 15 Mar 2019 14:15:32 -0600
Subject: Use TransitName for improved Pipe naming (#1024)

This changes from using the chiselname annotation on Pipe.apply to
using an explicit TransitName. This results in an improved name for
created valid and bits registers.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>---
 src/main/scala/chisel3/util/Valid.scala | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala
index 7dcad2c7..4ba762b5 100644
--- a/src/main/scala/chisel3/util/Valid.scala
+++ b/src/main/scala/chisel3/util/Valid.scala
@@ -8,7 +8,6 @@ package chisel3.util
 import chisel3._
 import chisel3.core.CompileOptions
 import chisel3.experimental.DataMirror
-import chisel3.internal.naming.chiselName  // can't use chisel3_ version because of compile order
 
 /** A [[Bundle]] that adds a `valid` bit to some data. This indicates that the user expects a "valid" interface between
   * a producer and a consumer. Here, the producer asserts the `valid` bit when data on the `bits` line contains valid
@@ -109,7 +108,6 @@ object Pipe {
     * @param latency the number of pipeline stages
     * @return $returnType
     */
-  @chiselName
   def apply[T <: Data](enqValid: Bool, enqBits: T, latency: Int)(implicit compileOptions: CompileOptions): Valid[T] = {
     require(latency >= 0, "Pipe latency must be greater than or equal to zero!")
     if (latency == 0) {
@@ -120,7 +118,10 @@ object Pipe {
     } else {
       val v = RegNext(enqValid, false.B)
       val b = RegEnable(enqBits, enqValid)
-      apply(v, b, latency-1)(compileOptions)
+      val out = apply(v, b, latency-1)(compileOptions)
+
+      TransitName.withSuffix("Pipe_valid")(out, v)
+      TransitName.withSuffix("Pipe_bits")(out, b)
     }
   }
 
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