From 4f02a255866729e9b646061aecb5a8ebc8ab9f91 Mon Sep 17 00:00:00 2001
From: Paul Rigge
Date: Tue, 19 Feb 2019 17:58:46 -0800
Subject: Update README to reference the bootcamp (#1025)

* Update README to reference the bootcamp
* Place learning section higher
---
 README.md | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/README.md b/README.md
index 108304d6..02672ab5 100644
--- a/README.md
+++ b/README.md
@@ -105,6 +105,9 @@ brew install sbt verilator
 If you are migrating to Chisel3 from Chisel2, please visit
 [Chisel3 vs Chisel2](https://github.com/ucb-bar/chisel3/wiki/Chisel3-vs-Chisel2)
 
+### Resources for Learning Chisel
+* [Chisel Bootcamp](https://github.com/freechipsproject/chisel-bootcamp), a collection of interactive Jupyter notebooks that teach Chisel
+* [Chisel Tutorial](https://github.com/ucb-bar/chisel-tutorial), a collection of exercises utlizing `sbt`
 
 ### Data Types Overview
 These are the base data types for defining circuit wires (abstract types which
@@ -112,8 +115,6 @@ may not be instantiated are greyed out):
 
 ![Image](doc/images/type_hierarchy.png?raw=true)
 
-### [Chisel Tutorial](https://github.com/ucb-bar/chisel-tutorial)
-
 ## For Hardware Engineers
 This section describes how to get started using Chisel to create a new RTL
 design from scratch.
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