From 4a05c0235c3325a565e9c7a157a222453e997d41 Mon Sep 17 00:00:00 2001
From: Aditya Naik
Date: Tue, 12 Mar 2024 08:39:32 -0700
Subject: Add log

---
 log.org | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/log.org b/log.org
index 82cc8eae..3b3955fd 100644
--- a/log.org
+++ b/log.org
@@ -27,3 +27,17 @@
   to get =AbstractInterface[A] => AbstractInterface[B] =>
   AbstractInterface[C]= to work.
 - Next step will to be figure out multiple arities for =AbstractInterface=
+* [2024-03-07 Thu] realization
+- key realization this morning: there's a problematic muddling of two
+  separate things in chisel: the /content of the module body/ and
+  /scala-time computations/
+- verilog module bodies need to be simple,
+  post-scala-computation-representations of what computations actually
+  need to be in hardware.
+** consequences of this problem at sifive
+- diplomacy creates multiple levels of scala-time computations while
+  abstracting away the module body.
+  - lazymodule is the scala-time computation, lazymoduleimp is the verilog body
+- people need to insert shit into bodies of "modules" using InModuleBody
+- interface of resulting modules is indeterminable
+
-- 
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