From 077aa80ea61b8517ef13f72d1fa3bec2aaa3063b Mon Sep 17 00:00:00 2001
From: Howard Mao
Date: Mon, 20 Jun 2016 13:44:08 -0700
Subject: make sure MuxCase and MuxLookup can take all subclasses of Data
 (#222)

---
 src/main/scala/chisel/util/Mux.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/main/scala/chisel/util/Mux.scala b/src/main/scala/chisel/util/Mux.scala
index 6f074a7e..04b174e9 100644
--- a/src/main/scala/chisel/util/Mux.scala
+++ b/src/main/scala/chisel/util/Mux.scala
@@ -40,7 +40,7 @@ object MuxLookup {
     * @param mapping a sequence to search of keys and values
     * @return the value found or the default if not
     */
-  def apply[S <: UInt, T <: Bits] (key: S, default: T, mapping: Seq[(S, T)]): T = {
+  def apply[S <: UInt, T <: Data] (key: S, default: T, mapping: Seq[(S, T)]): T = {
     var res = default
     for ((k, v) <- mapping.reverse)
       res = Mux(k === key, v, res)
@@ -54,7 +54,7 @@ object MuxCase {
   /** @param default the default value if none are enabled
     * @param mapping a set of data values with associated enables
     * @return the first value in mapping that is enabled */
-  def apply[T <: Bits] (default: T, mapping: Seq[(Bool, T)]): T = {
+  def apply[T <: Data] (default: T, mapping: Seq[(Bool, T)]): T = {
     var res = default
     for ((t, v) <- mapping.reverse){
       res = Mux(t, v, res)
-- 
cgit v1.2.3


From 70a41e5aed5dc3bc52133aecf46049a5946d33fe Mon Sep 17 00:00:00 2001
From: Howard Mao
Date: Mon, 20 Jun 2016 16:00:19 -0700
Subject: fix BlackBox setRefs to correctly handle arbitrarily nested bundles
 as ports (#223)

---
 chiselFrontend/src/main/scala/chisel/core/BlackBox.scala | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/chiselFrontend/src/main/scala/chisel/core/BlackBox.scala b/chiselFrontend/src/main/scala/chisel/core/BlackBox.scala
index 2126ebce..0e4c7a0c 100644
--- a/chiselFrontend/src/main/scala/chisel/core/BlackBox.scala
+++ b/chiselFrontend/src/main/scala/chisel/core/BlackBox.scala
@@ -28,13 +28,21 @@ abstract class BlackBox extends Module {
 
   // Do not do reflective naming of internal signals, just name io
   override private[core] def setRefs(): this.type = {
-    for ((name, port) <- ports) {
-      port.setRef(ModuleIO(this, _namespace.name(name)))
-    }
     // setRef is not called on the actual io.
     // There is a risk of user improperly attempting to connect directly with io
     // Long term solution will be to define BlackBox IO differently as part of
     //   it not descending from the (current) Module
+    for ((name, port) <- ports) {
+      port.setRef(ModuleIO(this, _namespace.name(name)))
+    }
+    // We need to call forceName and onModuleClose on all of the sub-elements
+    // of the io bundle, but NOT on the io bundle itself.
+    // Doing so would cause the wrong names to be assigned, since their parent
+    // is now the module itself instead of the io bundle.
+    for (id <- _ids; if id ne io) {
+      id.forceName(default="T", _namespace)
+      id._onModuleClose
+    }
     this
   }
 
-- 
cgit v1.2.3