From 37bfa06ae7e1dba3c55a1da84b9390d347446953 Mon Sep 17 00:00:00 2001
From: Christopher Celio
Date: Thu, 1 Oct 2015 22:50:41 -0700
Subject: Update README with Mem(seqRead) -> SeqMem()

---
 README.md | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/README.md b/README.md
index c6d5f2b1..68972c2d 100644
--- a/README.md
+++ b/README.md
@@ -17,6 +17,21 @@ modifications are:
    val wire = Wire(Bits(width = 15))
    ```
 
+ - Sequential memories:
+   ```
+   val addr = Reg(UInt())
+   val mem = Mem(UInt(width=8), 1024, seqRead = true)
+   val dout = when(enable) { mem(addr) }
+   ```
+   becomes (in Chisel3):
+   ```
+   val addr = UInt()
+   val mem = SeqMem(1024, UInt(width=8))
+   val dout = mem.read(addr, enable)
+   ```
+   Notice the address register is now internal to the SeqMem(), but the data
+   will still return on the subsequent cycle. 
+  
 ## Getting Started
 
 ### Overview
-- 
cgit v1.2.3