From 369bb6ece49dfb75de2a1d7784298477d60e7bcb Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Tue, 23 Jun 2020 16:49:05 -0400 Subject: Don't run FIRRTL in FlattenSpec's ChiselStage (#1493) Fix a bug in FlattenSpec where ChiselStage was running the FIRRTL compiler in ChiselStage and then re-running the FIRRTL compiler. This changes it to be like InlineSpec and to not run FIRRTL during ChiselStage. This was manually backported to 3.3.x. Signed-off-by: Schuyler Eldridge --- src/test/scala/chiselTests/InlineSpec.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/test/scala/chiselTests/InlineSpec.scala b/src/test/scala/chiselTests/InlineSpec.scala index 2d9bd792..fae927ec 100644 --- a/src/test/scala/chiselTests/InlineSpec.scala +++ b/src/test/scala/chiselTests/InlineSpec.scala @@ -72,7 +72,7 @@ class InlineSpec extends AnyFreeSpec with ChiselRunners with Matchers { "should compile to low FIRRTL" - { val chiselAnnotations = chiselStage - .execute(Array("-X", "low", "--target-dir", "test_run_dir"), + .execute(Array("--no-run-firrtl", "--target-dir", "test_run_dir"), Seq(ChiselGeneratorAnnotation(() => new Top))) chiselAnnotations.collect{ case a: FlattenAnnotation => a} should have length(1) -- cgit v1.2.3