From 153ef841e4bd76113736202460de906b4af1138a Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Tue, 1 Nov 2016 12:32:35 -0700
Subject: Update "alpha" references to "beta".

---
 README.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/README.md b/README.md
index 983f2b68..531fe67e 100644
--- a/README.md
+++ b/README.md
@@ -1,6 +1,6 @@
 # Chisel3
 Chisel3 is a new FIRRTL based chisel.
-It is currently in ALPHA VERSION, so many Chisel features may change in the coming months.
+It is currently in BETA VERSION, so some Chisel features may change in the coming months.
 
 Please visit the [Wiki](https://github.com/ucb-bar/chisel3/wiki) for a more
 detailed description.
@@ -52,7 +52,7 @@ This will walk you through installing Chisel and its dependencies:
 - [sbt](http://www.scala-sbt.org/), which is the preferred Scala build system
   and what Chisel uses.
 - [FIRRTL](https://github.com/ucb-bar/firrtl), which compile Chisel's IR down
-  to Verilog. A alpha version of FIRRTL written in Scala is available.
+  to Verilog. A beta version of FIRRTL written in Scala is available.
   - FIRRTL is currently a separate repository but may eventually be made
     available as a standalone program through system package managers and/or
     included in the Chisel source tree.
-- 
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