From 9ea57e031f834841609a30031ddab08fe4f47029 Mon Sep 17 00:00:00 2001
From: Carlos Eduardo
Date: Thu, 11 Mar 2021 18:25:54 -0300
Subject: Import memory files inline for Verilog generation (#1805)

This annotation adds memory import with inline generation for the
emmiter.
Supports both readmemh and readmemb statements based on argument.---
 .gitignore | 3 +++
 1 file changed, 3 insertions(+)

(limited to '.gitignore')

diff --git a/.gitignore b/.gitignore
index 5e727151..5da2d258 100644
--- a/.gitignore
+++ b/.gitignore
@@ -15,3 +15,6 @@ test_run_dir
 *~
 \#*\#
 .\#*
+.metals
+.bloop
+metals.sbt
-- 
cgit v1.2.3