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generation of annotations in a chisel circuit that could be used by custom firrtl passes
This spec also shows and tests in a limited way the new API of .signalName, .pathName, parentModName which allows access to the various path information of a chisel component (something that subclasses SignalId, most prominently SubClasses of Data and Module
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* signalName: returns the chirrtl name of the signal
* pathName: returns the full path name of the signal from the top module
* parentPathName: returns the full path of the signal's parent module instance from the top module
* parentModName: returns the signal's parent **module(not instance)** name.
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* Make "def width" a private API; expose isWidthKnown instead
Resolves #256.
Since width was used to determine whether getWidth would succeed, I added
def isWidthKnown: Boolean
but another option would be to expose something like
def widthOption: Option[Int]
...thoughts?
* Document getWidth/isWidthKnown
* Add widthOption for more idiomatic Scala manipulation of widths
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The API allowed this before, but not safely, as users could create
name conflicts. This exposes the pre-deduplication/sanitization
naming API, and closes the other one.
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This has been deprecated for a long time now (and really shouldn't
have existed to begin with).
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For Chisel nodes defined in Module class-level values of type Option or
Iterable, we can still use reflection to assign names based on the name
of the value. This works for arbitrary nesting of Option and Iterable so
long as the innermost type is HasId. Note that this excludes Maps which
always have an innermost type of Tuple2[_,_].
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For reasonable circuit delay, need to divide & conquer.
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package/folder, move more things into utils
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* chiselTests: include an example of two empty Vectors killing FIRRTL
* Aggregate: fix a bug whereby Vec[T] was using equals/hashCode of Seq
In Chisel, two vectors are NOT equal just if their contents are equal.
For example, two empty vectors should not be considered equal. This
patch makes Vec use the HasId._id for equality like other Chisel types.
Without this fix, Bundle.namedElts.seen: HashSet[Data]() will eliminate
one of the named vectors and emit bad IR.
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Source locators
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This prevents Verilator from erroring when it cannot determine the top-module.
It also changes the PRINTF_COND guard to correctly use the top-level reset
instead of just the top of the Chisel-generated code.
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chisel-testers repo
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for source locator macros
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Closes #90
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Partially resolves #164
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@aswaterman closes #156
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Setting the io ref there wasn't doing anything meaningful
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The old blackbox behavior still emitted extmodules that have a
clk, reset pin and prepended all io's with io_ (ultimately). Most
verilog modules do not follow this distinction (or use a slightly
different name for clock and so on).
Thus, instead BlackBox has been rewritten to not assume a clk or
reset pin. Instead, the io Bundle specified is flattened directly
into the Module.ports declaration. The tests have been rewritten
to compensate for this. Also, added a test that uses the clock pin.
As a secondary change, the _clock and _reset module parameters were
bad for two reasons. One, they used null as a default, which is a
scala best practices violation. Two, they were just not good names.
Instead the primary constructor has been rewritten to take an
Option[Clock] called override_clock and an Option[Bool] called
override_reset, which default to None. (Note how the getOrElse call
down below is much more natural now.)
However, users may not want to specify the Some(their_clock) so I
also added secondary constructors that take parameters named clock
and reset and wrap them into Some calls into the primary constructor.
This is a better UX because now you can just stipulate clock=blah in
instantiation of that module in symmetry with using the clock in the
definition of the module by invoking clock.
PS: We could also back out of allowing any overrides via the Module
constructor and just require the instantiating Module to do
submodule.clock := newclock, etc.
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