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2019-05-09Add Lfsr testsSchuyler Eldridge
Add LFSR tests using LFSR16 testing infrastructure. This also adds tests that are the same as the examples shown for LFSR scaladoc. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-09Add chisel3.util.random lib w/ LFSR generatorSchuyler Eldridge
Builds out PRNG and LFSR type hierarchy. PRNG is the base class of LFSR of which Galois and Fibonacci are concrete implementations. PRNGs contain state (a UInt) and an update (delta) function. They have a compile-time optional seed to set the PRNG state. The seed/state can also be set at run-time. PRNGs can be run-time parameterized based on how many updates they should do per cycle and whether or not to send the seed through step-count state updates before loading it. (h/t @jwright6323) LFSRs are parameterized in a reduction operation (XOR or XNOR). An LFSR that does NOT have a seed will be automatically initialized to a minimally safe state (set/reset one bit) based on their reduction operation. (h/t @aswaterman) Adds Galois and Fibonacci LFSRs that define appropriate update functions. Companion objects provide helpers to automatically generate maximal period variants. Taps are provide for a very large set of widths. The LFSR companion object provides an apply method to generate a Fibonacci LFSR random variable (like the old LFSR16).
2019-05-08Genericize LFSR testing infrastructureSchuyler Eldridge
Make LFSR testing generic to enable it to test other LFSRs. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-05Expand upon ScalaDoc in Driveredwardcwang
2019-05-01Make asTypeOf work for bundles with zero-width fields. (#1079)Paul Rigge
Closes #1075.
2019-04-26Bundle literals implementation (#1057)Richard Lin
2019-04-24Add back Int forms of Mem do_apply methods (#1082)Jack Koenig
This is necessary to support code that imports an implicit conversion from Int to UInt
2019-04-23Change size of memories from Int to BigInt (#1076)Jack Koenig
2019-04-19Fix wrong directionality for Vec(Flipped())Edward Wang
Create Chisel IR Port() in a way that Converter is happy with. Also add more extensive test suite for future-proofing. Close #1063
2019-04-15Avoid silently truncating BigInt to IntAndrew Waterman
- Introduce internal helper `castToInt`, which issues an error when the input BigInt can't be represented as Int. - Use `castToInt` wherever we were using `toInt` in a potentially unsafe way.
2019-04-12Implement connectFromBits in ChiselEnum (#1052)Jack Koenig
This is necessary to use ChiselEnum in aggregates where things are casted using .asTypeOf
2019-04-01Detect bundle aliasing (#1050)Richard Lin
2019-03-29Ignore empty aggregates elements when binding aggregate direction (#946)Jack Koenig
Previously, including an empty aggregate in a Bundle would cause a MixedDirectionAggregateException because it has no elements and thus doesn't have a direction * Add SampleElementBinding for Vec sample elements * Add ActualDirection.Empty for bound empty aggregates
2019-03-25Allow naming annotation to work outside builder context (#1051)Richard Lin
2019-03-25Check field referential equality in autoclonetype (#1047)Richard Lin
2019-03-23move doNotDedup to experimental (#1008)Sequencer
2019-03-22Fix enum annotations (#936)Hasan Genc
* Turned off strong enum annotations because they weren't working with Vec indexes * Add new EnumVecAnnotation for vecs of enums and vecs of bundles with enum fields * Changed Clock's width parameter back to a fixed constant value of 1 * Fixed enum annotations for Vecs of Bundles which contain enum elements * Fixed usage of "when/otherwise" to use consistent style
2019-03-21Remove @chiselName from MixedVec (#1045)Richard Lin
2019-03-18Split #974 into two PRs - scalastyle updates (#1037)Jim Lawson
* Update style warnings now that subprojects are aggregated. Use "scalastyle-test-config.xml" for scalastyle config in tests. Enable "_" in method names and accept method names ending in "_=". Re-sync scalastyle-test-config.xml with scalastyle-config.xml * Remove bogus tests that crept in with git add * Add missing import.
2019-03-15Merge branch 'master' into popcountedwardcwang
2019-03-15Use TransitName for improved Pipe naming (#1024)Schuyler Eldridge
This changes from using the chiselname annotation on Pipe.apply to using an explicit TransitName. This results in an improved name for created valid and bits registers. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-03-15Add width constraint to PopCount test (which currently fails)Andrew Waterman
2019-03-15Add PopCount testAndrew Waterman
2019-03-14Decouple implementation details from LoadMemoryAnnotation. (#1034)Jim Lawson
2019-03-11ScalaDocs improvement for utils Math, MixedVec (#1019)Richard Lin
2019-02-25Docs for ListLookup (#1028)Richard Lin
Co-Authored-By: ducky64 <elpato25@gmail.com> Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@gmail.com> Co-Authored-By: Edward Wang <edward.c.wang@compdigitec.com>
2019-02-19Add HasBlackBoxPath to BlackBoxUtils.scala (#903)Albert Chen
* Add HasBlackBoxPath trait * Use 'setResource' instead of 'addResource' * Add ScalaDoc
2019-02-19ScalaDoc for Mux (examples added) (#1014)Martin Schoeberl
Co-Authored-By: schoeberl <martin@jopdesign.com> Co-Authored-By: Edward Wang <edward.c.wang@compdigitec.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-02-19Add TransitNameSpecSchuyler Eldridge
This adds a test of chisel3.util.TransitName (which is used for the TransitName documentation). Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-02-19Add Scaladoc for chisel3.util.TransitNameSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-02-19Mainline Chisel multi-clock functionality (#1013)edwardcwang
Close #1009
2019-02-19Util doc lsfr (#1021)Chick Markley
* Update documentation for LSFR16 - Moved bulk of comments to object. - Added an example - Added functional test - example based on section of test * Update documentation for LSFR16 - Moved bulk of comments to object. - Added an example - Added functional test - example based on section of test * Update documentation for LSFR16 - Fixed typos in LFSR - Reduce trials a little - Add test of LFSR period * Update documentation for LSFR16 - Fixed remaining LSFR, arrgh - Removed intellij specific warning suppressor - Fixed comments/scaladoc wording and case. * Update documentation for LSFR16 - Use printable interpolator as example of printing out a Vec
2019-02-19Documentation for Reg utilities (#1018)Martin Schoeberl
2019-02-19ScalaDoc for OneHot (#1016)Martin Schoeberl
2019-02-18Add requirement that Pipe latency >= 0Schuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-02-18Add Scaladoc for chisel3.util.PipeSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-02-18Add Scaldoc for chisel3.util.ValidSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-02-01Queue TestsBrendan Sweeney
2019-01-25WireDefault instead of WireInit, keep WireInit around (#986)Martin Schoeberl
2019-01-23Bump copyright year (#997)Jim Lawson
2019-01-22Define Data .toString (#985)Richard Lin
toString on Data subtypes will now print the type and optionally binding information including literals and IO names as feasible.
2019-01-22Changes to BoringUtils Scaladoc, paramater nameSchuyler Eldridge
This compresses the Scaladoc for BoringUtils slightly by using 120 character lines and removing unnecessary whitespace. This also changes the poorly named "dedup" parameter to the what it actually is: "disableDedup". Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-01-22Fix BoringUtilsSpec to require no dedupSchuyler Eldridge
This adds two tests to the BoringUtilsSpec to explicitly verify that deduplication is required when boring. This adds tests that both verify that the test passes as expected with deduplication enabled and that the same test fails with deduplication disabled. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-01-22Fix BoringUtils deduplication bugSchuyler Eldridge
This fixes a bug where BoringUtils non-hierarchical sinks would be deduplicated even when specified that they should not be. h/t @ucbjrl for discovering this! Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-01-22Add Rocket Chip-style clonemodule as CloneModuleAsRecord to experimental (#943)Albert Magyar
2019-01-21Support DontCare in Mux and cloneSupertype (#995)Richard Lin
2019-01-21Unify internal (chisel3.core) and external (chisel3 / chisel3.experimental) ↵Richard Lin
Module class names (#994)
2019-01-11Add test for chiselNaming of Seq[Data]Andrew Waterman
2019-01-09Avoid procedural wire assignment in test resourceSchuyler Eldridge
Verilator 4.008 dropped the hammer on procedural wire assignment to align with the IEEE standard (first I've heard of this, though). The VerilogVendingMachine.v test resource will error in Verilator 4.008 with a PROCASSWIRE error if you try to compile it. This fixes that example to only assign to a register. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-01-07Fix build error due to scala bug #11125 (#967)Nick Hynes
JDK 11 `java.lang.String#lines` conflicts with Scala `StringOps#lines`. This has been fixed in scalac 2.12.8 but projects using 2.11 in their cross-build need the `Predef.augmentString` patch. [Scala bug & fix reference](https://github.com/scala/bug/issues/11125)
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