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2019-09-16Da steve101 tree reduce (#485)Jack Koenig
* Add a tree reduce function to Vec * Change function names of reduce operation function in Vec * Change reference to single layer operation in Vec.reduce * Commint name change for pair macro * Remove pair, call not necessary and can just be used from grouped(2) and map * Changed to reduceTree, added default identity function for single reduce. * Change style of Vec.reduceTree and tests to chisel3 and canonical Scala style * Cleanup Vec initialization, implicitCompileOptions
2019-09-13Add requirements to Queue class (#1176)Jack Koenig
FIRRTL barfs on negative and zero-sized memories
2019-09-13Fix Queue.apply for size 0 in chisel3._ code (#1177)Jack Koenig
2019-09-11Move dontTouch, RawModule, and MultiIOModule out of experimental (#1162)Jim Lawson
* Move dontTouch out of experimental package. * Move RawModule, MultiIOModule out of experimental. * Respond to comments - Move LagacyModule from experimental to internal. *NOTE*: At some point, these module definitions (especially those in separate packages) should be moved to individual files at the appropriate location in the source tree. The current organization is purely to support comparison with prior versions. * Fix up a few more imports.
2019-08-27Test stack trace trimming for ChiselStageSchuyler Eldridge
Use FIRRTL stage-style testing to check stdout printing without and with --full-stacktrace. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-08-27Enable --module command line argumentSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-08-27Move stack trimming from Driver to ChiselStageSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-08-27Add test that stack trace trimming worksSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-08-27Remove stack trace trimming in Elaborate phaseSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-08-27Add firrtlTests.Utils methodsSchuyler Eldridge
This adds methods for examining stdout/stderr and exit codes inside of a Scala program. This are pulled directly from firrtlTests, but we aren't currently publishing those anywhere that we can get at them. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-08-13Use a PhaseManager for Driver internalsSchuyler Eldridge
Migrate Driver to use a PhaseManager to internally resolve Phase ordering. This requires the use of an identity node to adequately describe the necessary prerequisite/dependents. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2019-08-13Migrate ChiselStage to use the DependencyAPISchuyler Eldridge
Modifies ChiselStage to use a PhaseManager for Phase ordering. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2019-08-13Add Dependencies for Chisel PhasesSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2019-08-13Add support for asynchronous reset (#1011)Jack Koenig
Adds new AsyncReset and "abstract" Reset types. Reset is inferred in FIRRTL to be either AsyncReset or Bool. The "reset type" of a register is set by the type of its reset signal: val asyncReset: AsyncReset = IO(Input(AsyncReset())) val syncReset: Bool = IO(Input(Bool())) val abstractReset: Reset = IO(Input(Reset())) val asyncReg = withReset(asyncReset) { RegInit(0.U) } val syncReg = withReset(syncReset) { RegInit(0.U) } val inferredReg = withReset(abstractReset) { RegInit(0.U) } AsyncReset can be cast to and from Bool. Whereas synchronous reset is equivalent to a mux in front of a flip-flop and thus can be driven by logic, asynchronous reset requires that the reset value is a constant. This is checked in FIRRTL. Inference of the concrete type of a Reset occurs based on the type the Reset's drivers. This inference is very simple, it is simple forward propagation of the type, but it allows for writing blocks and modules that are agnostic to the reset type. In particular, the implicit `reset` value in MultiIOModule and thus Module is now concretely an instance of Reset and thus will be inferred in FIRRTL.
2019-08-12Aspect-Oriented Programming for Chisel (#1077)Adam Izraelevitz
Added Aspects to Chisel, enabling a mechanism for dependency injection to hardware modules.
2019-08-08Require target is hardware for Vec.apply(a: UInt)Schuyler Eldridge
Adds a check that a Vec being indexed by a UInt is, in fact, a hardware type. This includes a test for this. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-08-06Avoid when(reset) construct in LFSRAndrew Waterman
Muxes and resets are only isomorphic with synchronous reset. Use a reset instead of a conditional to make this async-reset-safe.
2019-08-01Flatten *FactoryBase hierarchySchuyler Eldridge
This renames all *FactoryBase traits to *Factory, removes transparent *Factory objects, and propagates this flattened hierarchy throughout the codebase. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-08-01Remove anything deprecated since before 3.2Schuyler Eldridge
Anything removed by this that is used by the compatibility layer is migrated to the compatibility layer. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Fix deprecated Vec usage in chisel3.util.LFSR16Schuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Add SInt deprecated compatibility testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Add UInt deprecated compatibility testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Add Bits deprecated compatibility testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Add VecLike deprecated compatibility testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Add Wire deprecated compatibility testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Add Data deprecated compatibility testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Add debug deprecated compatibility testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Add Mem/SeqMem deprecated compatibility testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Add LFSR16 deprecated compatibility testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Add Queue deprecated compatibility testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Add Enum deprecated compatibility testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Add BitPat deprecated compatibility testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Fixup and enable Dummy CompatibilitySpec testSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-18Support Analog DontCare bulk-connect (#1056)Richard Lin
Short-term patch to enable this useful behavior. In the future, we may want to rearchitect the type system and/or rethink the more edge-case connect behavior.
2019-07-18Add width utility functions to avoid incorrect usage of bare log2Ceil(). (#819)Jim Lawson
* Add width utility functions to avoid incorrect usage of bare log2Ceil(). * Respond to comments: Remove apply(Data) method. Change name(s) to signedBitLength, unsignedBitLength. * Respond to comments - don't be lazy. Independently calculate the bit length to verify correct operation. * Respond to comments - return in.bitLength - 0 (not 1) for 0 * Respond to comments - update wdith for signed 0; add explicit tests. * Add comment expressing zero width wire assumption.
2019-06-24Changed Value macro in ChiselEnum so that it doesn't use deprecated (#1104)Hasan Genc
function. This also fixes prior issue where ChiselEnums would not compile when @chiselName was applied to a module containing a ChiselEnum
2019-06-11Added documentation to Decoupled, Conditionals, Counter (#1015)Adam Izraelevitz
* Added documentation to Decoupled, Conditionals, Counter * Fixed private Counter class error * Move Counter class deprecation and re-definition into util package object. * Revert "Move Counter class deprecation and re-definition into util package object." This reverts commit f61bdddf7051522363e1d203fcd46b512047c87d. * Restore the old Counter definition and address this in a separate PR. We can move the deprecation warning and the type definition into the util package object (see f61bdddf7051522363e1d203fcd46b512047c87d), but then we fail tests using Counter with a `ScalaReflectionException` in Aggregate.scala:779 (in def cloneType) when: `Some(mirror.reflect(this).symbol)` generates `type Counter is not a class`. * Made @ducky64 change to Counter doc Used to generate an inline (logic directly in the containing Module, no internal Module is created) hardware counter.
2019-05-22Make Driver a ChiselStage compatibility layerSchuyler Eldridge
This converts the original chisel3.Driver to use chisel3.stage.ChiselStage. This is implemented in the following way: 1. ExecutionOptions are converted to an AnnotationSeq 2. The AnnotationSeq is preprocessed using phases contained in the Chisel DriverCompatibility objects. One of these *disables* the execution of FirrtlStage by ChiselStage. 3. ChiselStage runs on the preprocessed AnnotationSeq 4. The input ExecutionOptionsManager is mutated based on the output of ChiselStage. 5. The FIRRTL stage is re-enabled if it's supposed to run and selected FIRRTL DriverCompatibility phases run. 6. FirrtlStage runs 7. The output AnnotationSeq is "viewed" as a ChiselExecutionResult This modifies the original DriverSpec to make it more verbose with the addition of info statements. The functionality of the DriverSpec is unmodified. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-22Add toAnnotations method to ChiselExecutionOptionsSchuyler Eldridge
Adds a method to enable conversion from ChiselExecutionOptions back to an AnnotationSeq. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-22Add Driver Compatibility LayerSchuyler Eldridge
This includes phases necessary to provide backwards compatibility with the old Chisel3 Driver. These are placed in a DriverCompatibility object inside chisel3.stage.phases. The following four phases are included: - AddImplicitOutputFile (from a TopNameAnnotation) - AddImplicitOutputAnnotationFile phase - DisableFirrtlStage (to disable ChiselStage running FirrtlStage) - MutateOptionsManager (to update options after ChiselStage) - ReEnableFirrtlStage (to renable FirrtlStage if needed) Additionally, this adds a view of a ChiselExecutionResult for providing the legacy return type of the Chisel Driver. Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-Authored-By: chick <chick@qrhino.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-22Add chisel3.stage.ChiselStageSchuyler Eldridge
This adds ChiselStage, a reimplementation of chisel3.Driver as a firrtl.options.Stage. This is simplistically described as a pipeline of Phases. Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-Authored-By: chick <chick@qrhino.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-22Add chisel3.stage.phases.MaybeFirrtlStageSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2019-05-22Add stage.phases.AddImplicitOutputAnnotationFileSchuyler Eldridge
Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-Authored-By: chick <chick@qrhino.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-22Add chisel.stage.phases.AddImplicitOutputFileSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-22Add chisel3.stage.phases.Emitter PhaseSchuyler Eldridge
This adds an Emitter Phase that writes a ChiselCircuitAnnotation to a file if a ChiselOutputFileAnnotation is present. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-22Add chisel3.stage.phases.Convert PhaseSchuyler Eldridge
This coalesces three distinct operations into one Convert Phase: 1. Chisel Circuit to FIRRTL Circuit (CHIRRTL) conversion 2. Conversion of Chisel Annotations to FIRRTL Annotations 3. Generation of RunFirrtlTransformAnnotations Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-Authored-By: chick <chick@qrhino.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-22Add chisel3.stage.phases.Elaborate PhaseSchuyler Eldridge
This adds an Elaborate Phase that expands ChiselGeneratorAnnotations into ChiselCircuitAnnotations and deletes the original. Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-Authored-By: chick <chick@qrhino.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-22Add chisel3.stage.phases.Checks PhaseSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-22Add ChiselOptionsViewSchuyler Eldridge
Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-Authored-By: chick <chick@qrhino.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-22Add chisel3.stage.ChiselOptionsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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