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This makes the resulting Verilog from decoding a TruthTable deterministic.
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preserves input/output information of the type being reduced.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Co-authored-by: Megan Wachs <megan@sifive.com>
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Co-authored-by: Jack Koenig <koenig@sifive.com>
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* DataProducts for Seq and Tuple2-10 in DataProduct companion object
* DataViews for Seq and Tuple 2-10 in DataView companion object
* HWTuple2-10 Bundles in chisel3.experimental
* Implicit conversions from Seq to Vec and Tuple to HWTuple in chisel3.experimental.conversions
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Provides a more intuitive implementation of toString for Data.
Utilizes the fact that the compiler plugin provides names earlier than
Chisel had in the past so we can accurately guess the name of
signals even in the currently elaborating module.
Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Jack Koenig <jack.koenig3@gmail.com>
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As the chisel3 compiler plugin is now required, we can delete unused
code for reflective autoclonetype as well as the noPluginTests.
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* Bugfix - definition name index skipping with D/I
* Add tests to DefinitionSpec
* Add failing test
* Fix failing test
* Update core/src/main/scala/chisel3/internal/Builder.scala
Co-authored-by: Jack Koenig <jack.koenig3@gmail.com>
* whitespace
* revert package private val
Co-authored-by: Jack Koenig <jack.koenig3@gmail.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
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This fixes CI which fails with current firrtl 1.5-SNAPSHOT.
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These were not actually deprecated but any APIs using them were long
since deprecated and more recently removed.
They also depend on long deprecated APIs in FIRRTL that will soon be
removed.
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Also remove as many deprecated APIs as possible by inlining
implementations of old deprecated/removed code from firrtl
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* refactor Queue.hasFlush: Boolean to Queue.flush: Option[Bool].
Using factory Queue(..., hasFlush = true) won't take effects, since in the Queue.apply API, Queue Module is not exposed, thus even user defines hasFlush = true, there is no place for them to give the flush signal.
This commit fix this, refactor Queue.hasFlush: Boolean to Queue.flush: Option[Bool], makes user be able to pass the flush signal into Queue Module.
* use zip to connect.
* refactor docs.
Co-authored-by: Megan Wachs <megan@sifive.com>
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* Update Arbiter.scala
* Update src/main/scala/chisel3/util/Arbiter.scala
changed group name
Co-authored-by: Megan Wachs <megan@sifive.com>
* minor changes on grouping ArbiterIO
* removed unmatched closing brace
* Remove groupdesc from Arbiter.scala
* Added groupdesc to Aggregate.scala
* Update Arbiter.scala
* Update core/src/main/scala/chisel3/Aggregate.scala
Co-authored-by: Megan Wachs <megan@sifive.com>
* Update Arbiter.scala
* Update src/main/scala/chisel3/util/Arbiter.scala
Added suugestions.
Co-authored-by: Megan Wachs <megan@sifive.com>
* added suggestions from review
* added suggestions from review
* Resolved conflicts
* update Arbiter.scala
* Update core/src/main/scala/chisel3/Aggregate.scala
deleted groudesc for ArbiterIO
Co-authored-by: Megan Wachs <megan@sifive.com>
* Update Scaladoc syntax
* removed some lines
* Better documentation
* Removed @param and @gen
* Update core/src/main/scala/chisel3/Aggregate.scala
Co-authored-by: Megan Wachs <megan@sifive.com>
* Update src/main/scala/chisel3/util/Arbiter.scala
Co-authored-by: Megan Wachs <megan@sifive.com>
* Added groupdesc to ArbiterIO
* Update src/main/scala/chisel3/util/Arbiter.scala
Co-authored-by: Megan Wachs <megan@sifive.com>
* Update core/src/main/scala/chisel3/Aggregate.scala
Co-authored-by: Megan Wachs <megan@sifive.com>
* Update Arbiter.scala
* Update src/main/scala/chisel3/util/Arbiter.scala
Co-authored-by: Megan Wachs <megan@sifive.com>
* Update Arbiter.scala
Co-authored-by: Megan Wachs <megan@sifive.com>
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* Add field grouping scaladocs for DecoupledIo
* Added groupdesc to DecoupledIO
* Added groupings for IrrevocableIO
* Add groupings for ValidIO
* Add field grouping scaladoc for PRNGIO
* Add field grouping scaladoc for QueueIO
* Added groupings for PipeIO
* Update src/main/scala/chisel3/util/Decoupled.scala
Commited Sugestion
Co-authored-by: Megan Wachs <megan@sifive.com>
* Update src/main/scala/chisel3/util/Decoupled.scala
Co-authored-by: Megan Wachs <megan@sifive.com>
* Update src/main/scala/chisel3/util/Decoupled.scala
Co-authored-by: Megan Wachs <megan@sifive.com>
* Update src/main/scala/chisel3/util/Decoupled.scala
Co-authored-by: Megan Wachs <megan@sifive.com>
* Update src/main/scala/chisel3/util/Decoupled.scala
Co-authored-by: Megan Wachs <megan@sifive.com>
* Update src/main/scala/chisel3/util/Valid.scala
Co-authored-by: Megan Wachs <megan@sifive.com>
* Update src/main/scala/chisel3/util/Valid.scala
Co-authored-by: Megan Wachs <megan@sifive.com>
* Update src/main/scala/chisel3/util/Valid.scala
Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Megan Wachs <megan@sifive.com>
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Exposing more internals of D/I, which are required for supporting D/I with more powerful Chisel libraries:
- Exposing IsClone[_]
- Exposing InstantiableClone[_]
- Gated builders for Instance/Definition
- Unsealing Lookupable, with protected accessors for proto and cloned
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* Add Hierarchy trait
* Add Hierarchy trait
* Add Hierarchy scaladoc
* Add license
* Add isA and tests
* Add back isA
* Add new Select APIs for hierarchy package
* Update scaladoc
* Write outlines for tests
* Add tests and fixes to new Select functions
* Make calculate via lazy val
* Apply suggestions from code review
Co-authored-by: Megan Wachs <megan@sifive.com>
* Apply suggestions from code review
Co-authored-by: Megan Wachs <megan@sifive.com>
* Clean up scaladoc
* Add shouldNot compile
* Apply suggestions from code review
Co-authored-by: Megan Wachs <megan@sifive.com>
* Bugfix all funcs should analyze root too
* Add mdoc, bugfix toDefinition
* Make func private, add scaladoc
* Update src/test/scala/chiselTests/experimental/hierarchy/InstanceSpec.scala
Co-authored-by: Jack Koenig <koenig@sifive.com>
* Made protected vals private
* Apply suggestions from code review
Co-authored-by: Jack Koenig <koenig@sifive.com>
* Address code review comments
* Added additional null check
Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
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* Add Hierarchy trait
* Add Hierarchy trait
* Add Hierarchy scaladoc
* Add license
* Add isA and tests
* Add back isA
* Make calculate via lazy val
* Apply suggestions from code review
Co-authored-by: Megan Wachs <megan@sifive.com>
* Add shouldNot compile
* Update src/test/scala/chiselTests/experimental/hierarchy/InstanceSpec.scala
Co-authored-by: Jack Koenig <koenig@sifive.com>
* Made protected vals private
Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Also replace all uses of .fire() with .fire
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In `Bits.scala`, `FixedPoint` and `Interval` did not defeine the `do_unary_-` methods (the `do_`) was missing
The recent PR #2124 combined with the above fact made DspTools break. This fix is necessary to get
that repo to build.
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* change static shift behavior to mod width when width is known
* add dynamic shift
* basic tests that actually do something
* MatchedRotateLeftAndRight based on the idea from @chick
* BasicRotate rotate "b001" and compare with known values
* Fix check for KnownWidth(0|1) as suggested by @aswaterman
* Add dontTouch to UIntOps.io (other tests were also optimized out)
Co-authored-by: Chick Markley <chick@qrhino.com>
Co-authored-by: Andrew Waterman <andrew@sifive.com>
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The removal of virtual method io accidentally made the naming of io in
compatibility mode Bundles sensitive to the prefix at the time of the
first access of the field. It also made .suggestName able to override
the name. This commit fixes that issue by forcing the name of the io
Data to be "io" no matter what.
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functions (#2124)
* Migrate nullary funcs to parameterless versions
* Make deprecation message and dummy arguments clear and consistent
Co-authored-by: Megan Wachs <megan@sifive.com>
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* Remove all manual cloneTypes and make it chisel runtime deprecated to add one
* runtime deprecate cloneType with runtime reflection
* [Backport this commit] Bundle: add check that override def cloneType still works (will be made an error later)
* Plugin: make it an error to override cloneType and add a test for that
* Docs: can't compile the cloneType anymore
* BundleSpec: comment out failing test I cannot get to fail or ignore
Co-authored-by: Jack Koenig <koenig@sifive.com>
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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This introduces a new experimental API for module instantiation that disentagles
elaborating the definition (or implementation) from instantiation of
a given module. This solves Chisel's longstanding reliance on
"Deduplication" for generating Verilog with multiple instances of the
same module.
The new API resides in package chisel3.experimental.hierarchy. Please
see the hierarchy ScalaDoc, documentation, and tests for examples of
use.
Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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Previous incomplete fixes in #2023 and #2031.
The legality of a FIRRTL connection is determined by type and flow.
Chisel does not have access to true flow information. Previous fix
attempts tried to use ActualDirection as a stand-in for flow, but it is
incorrect in many cases. This new approach checks the flows of the
lvalue and rvalues in the connect and flips the connection if either
the lvalue cannot be a sink or the rvalue cannot be a source.
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* add Y and N to BitPat.
* add ## for BitPat.
* add rawString API.
* use rawString in decoder
* add select and slice to BitPat.
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* replace custom model checker with chiseltest formal verify command
* integration-tests can make use of chiseltest
This is a compromise solution to avoid issues
with binary compatibility breaking changes in chisel3.
* ci: move integration tests into separate job
* run integration tests only for one scala version
* ci: install espresso for integration tests
* Update build.sbt
Co-authored-by: Jack Koenig <jack.koenig3@gmail.com>
Co-authored-by: Jack Koenig <jack.koenig3@gmail.com>
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This will be slightly slower as it involves converting from Chisel
modules to FIRRTL modules before turning them into Strings. This cost is
somewhat mitigated by doing that conversion lazily such that we never
materialize the entire firrtl Circuit in memory, only 1 module at a
time.
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Co-authored-by: Jack Koenig <koenig@sifive.com>
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There might be some "@"?
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(#1944)" (#2080)
This reverts commit ed894c61474c8bc73761a6c360ef9d14505d853b.
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* remove DefRegInit, change DefReg API with option defination.
* add error message
* use Option[RegInitIR].
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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