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AgeCommit message (Expand)Author
2019-05-22Add Driver Compatibility LayerSchuyler Eldridge
2019-05-22Add stage.phases.AddImplicitOutputAnnotationFileSchuyler Eldridge
2019-05-22Add chisel.stage.phases.AddImplicitOutputFileSchuyler Eldridge
2019-05-22Add chisel3.stage.phases.Emitter PhaseSchuyler Eldridge
2019-05-22Add chisel3.stage.phases.Convert PhaseSchuyler Eldridge
2019-05-22Add chisel3.stage.phases.Elaborate PhaseSchuyler Eldridge
2019-05-22Add chisel3.stage.phases.Checks PhaseSchuyler Eldridge
2019-05-22Add ChiselOptionsViewSchuyler Eldridge
2019-05-22Add chisel3.stage AnnotationsSchuyler Eldridge
2019-05-20Repackagecore rebase (#1078)Jim Lawson
2019-05-13RawModule with no reset should be able to use withClock method. (#1065)Chick Markley
2019-05-10Augment LFSR16 test to test the enable as wellAndrew Waterman
2019-05-09PRNG state UInt->Vec[Bool], make async reset safeSchuyler Eldridge
2019-05-09Fix treatment of Vec of Analog and Vec of Bundle of Analog (#1091)Jack Koenig
2019-05-09Deprecate LFSR16, use FibonacciLFSR internallySchuyler Eldridge
2019-05-09Add Lfsr testsSchuyler Eldridge
2019-05-09Add chisel3.util.random lib w/ LFSR generatorSchuyler Eldridge
2019-05-08Genericize LFSR testing infrastructureSchuyler Eldridge
2019-05-01Make asTypeOf work for bundles with zero-width fields. (#1079)Paul Rigge
2019-04-26Bundle literals implementation (#1057)Richard Lin
2019-04-24Add back Int forms of Mem do_apply methods (#1082)Jack Koenig
2019-04-23Change size of memories from Int to BigInt (#1076)Jack Koenig
2019-04-19Fix wrong directionality for Vec(Flipped())Edward Wang
2019-04-12Implement connectFromBits in ChiselEnum (#1052)Jack Koenig
2019-04-01Detect bundle aliasing (#1050)Richard Lin
2019-03-29Ignore empty aggregates elements when binding aggregate direction (#946)Jack Koenig
2019-03-25Allow naming annotation to work outside builder context (#1051)Richard Lin
2019-03-25Check field referential equality in autoclonetype (#1047)Richard Lin
2019-03-23move doNotDedup to experimental (#1008)Sequencer
2019-03-22Fix enum annotations (#936)Hasan Genc
2019-03-18Split #974 into two PRs - scalastyle updates (#1037)Jim Lawson
2019-03-15Add width constraint to PopCount test (which currently fails)Andrew Waterman
2019-03-15Add PopCount testAndrew Waterman
2019-02-19Add HasBlackBoxPath to BlackBoxUtils.scala (#903)Albert Chen
2019-02-19Add TransitNameSpecSchuyler Eldridge
2019-02-19Mainline Chisel multi-clock functionality (#1013)edwardcwang
2019-02-19Util doc lsfr (#1021)Chick Markley
2019-02-01Queue TestsBrendan Sweeney
2019-01-25WireDefault instead of WireInit, keep WireInit around (#986)Martin Schoeberl
2019-01-22Define Data .toString (#985)Richard Lin
2019-01-22Fix BoringUtilsSpec to require no dedupSchuyler Eldridge
2019-01-22Add Rocket Chip-style clonemodule as CloneModuleAsRecord to experimental (#943)Albert Magyar
2019-01-21Support DontCare in Mux and cloneSupertype (#995)Richard Lin
2019-01-11Add test for chiselNaming of Seq[Data]Andrew Waterman
2019-01-09Avoid procedural wire assignment in test resourceSchuyler Eldridge
2018-12-19Fix width inferencing issue (#952)Jack Koenig
2018-12-04Add asBool, deprecate toBoolJack Koenig
2018-12-04Add asBools, deprecate toBoolsJack Koenig
2018-12-04Make toBools support chained applyJack Koenig
2018-11-26Trim Stack Trace (#931)Albert Chen
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