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2020-09-22Support using switch without importing SwitchContext (#1595)Jack Koenig
2020-09-14Documentation and minor plugin changes. (#1573)Adam Izraelevitz
* Added documentation. Bugfix in plugin. Moved plugin APIs to separate package * Revert reg naming behavior (omit underscore) * Added documentation and a test * Addressed reviewer feedback.
2020-09-09Recursively generate one-hot multiplexers for aggregates (#1557)Jerry Zhao
Test all cases in ParameterizedOneHotTesters Co-authored-by: Jack Koenig <koenig@sifive.com>
2020-09-09Add new annotation for Chisel Circuit serialization (#1580)Jack Koenig
ChiselCircuitAnnotation no longer extends CustomFileEmission, rather it is Unserializable. Also the --chisel-output-file is added to the ChiselCli. New phase AddSerializationAnnotations constructs a CircuitSerializationAnnotation from ChiselCircuitAnnotation and ChiselOutputFileAnnotation. Both .fir and .pb file formats are supported. Default format is .fir unless a --chisel-output-file is specified with a .pb extension.
2020-09-09Fix load memory from file to work with binary (#1583)HappyQuark
* fix loadMemoryFromFile to work with binary Passed in hexOrBinary parameter to ChiselLoadMemoryAnnotation * Added test for binary format support in loadMemoryFromFile * Added test for binary format support in loadMemoryFromFile
2020-08-26Add ChiselPhase, Stop writing files in ChiselStage$ methods, Expand ↵Schuyler Eldridge
ChiselStage$ helpers (#1566) * Add ChiselPhase * Use ChiselPhase in ChiselStage, remove targets Switch from a one-off PhaseManager inside ChiselStage to actually using the newly added ChiselPhase. This removes the targets method (and API) from ChiselStage. * Stop writing to files in ChiselStage$ methods Change the ChiselStage companion object methods, elaborate and convert, to not write files. Under the hood, these are switched from using ChiselStage (which, like all phases, will write files) to using ChiselPhase. * Test that ChiselStage$ methods write no files Modify existing ChiselStage object method tests to check that no files are written. * Expand ChiselStage$ API with more helpers This adds additional methods to the ChiselStage object for going directly from a Chisel module to a string including: CHIRRTL, high FIRRTL IR, Verilog, and SystemVerilog. Differing from their ChiselStage class counterparts, these take no arguments other than the module and write no files. * Add tests of new ChiselStage$ helper methods * Use ChiselStage object in tests Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-08-13Move treadle dependency to the tests (#1554)Jack Koenig
Use inheritance to make TesterDriver Backend API extensible, then define a TreadleBackend in the test project
2020-08-13Allow counters to be reset manually (#1527)Josh Bassett
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-08-12Switch to HowToSerialize for Emission (#1405)Schuyler Eldridge
* Fix emit{Firrtl,Verilog} for CustomFileEmission Change ChiselStage helper methods for emitting FIRRTL (emitFirrtl) and Verilog (emitVerilog) to look for Circuit and Verilog annotations instead of DeletedAnnotations. This is needed after migrating to the CustomFileEmission mixin in FIRRTL where FIRRTL will no longer delete emitter annotations. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Use CustomFileEmission for ChiselCircuitAnnotation Removes the explicit chisel3.phases.Emitter and instead does emission with a CustomFileEmission mixin to ChiselCircuitAnnotation. This then prevents the need for passing around DeletedAnnotations. As a consequence, I removed an unnecessary run of a second Converter in the Driver. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Fix tests for use of CustomFileEmission trait Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Fixes for newer CustomFileEmission API Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-08-11Bug fix for manipulating submodules in aspects (#1538)Justin Deters
* Fixed the aspect as parent bug in Data and MonoConnect * refactored and cleaned up finding an aspect parent * Added aspect fix to the BiConnect class * added unit test for manipulating submodules via aspects * Refactored to move determination of proper parent to Builder and made logic simpler in MonoConnect, Data, and BiConnect * Removed unused function and provided Scaladoc for retrieveParent
2020-08-11Restore Counter.n API (#1546)Jack Koenig
Includes special case support for Counter(0) which has identical behavior to Counter(1) except for the value of n.
2020-07-31Check whether signals escape their when scopes (#1518)Albert Magyar
* Include and check when scoping as part of reg/mem/wire/node bindings * Allow outdated 'when' behavior of CHIRRTL memory ports with enables * Extend cross-module / when-visibility checks to all data refs * Fixes #1512 * Cannot be checked if outside a module context * E.g. delayed evaluation of printf / assert args * Add basic test cases for cross-module refs / signals escaping when scopes * Remove illegal cross-module references from existing tests
2020-07-30Broken auto-clonetype on Scala 2.11.12 (#1480)Adam Izraelevitz
* Added broken auto-clonetype test * Added bugfix for 2.11 * Add descriptive comment for 2.11 special case * Update src/test/scala/chiselTests/AutoClonetypeSpec.scala * Update src/test/scala/chiselTests/AutoClonetypeSpec.scala Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-07-30Allow a counter to be instantiated using a Scala range (#1515)Josh Bassett
* Add positive range generator * Allow the Counter module to be instantiated with a Scala range * Use head/last to determine counter width Co-authored-by: Jack Koenig <jack.koenig3@gmail.com> * Let counter overflow naturally when appropriate We only need to explicitly wrap counters that don't start at zero, or end on a power of two. Otherwise we just let the counter overflow naturally to avoid wasting an extra mux. * Require counter range to be non-empty Co-authored-by: Jack Koenig <jack.koenig3@gmail.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-07-29Improved Chisel Naming via Compiler Plugins + Prefixing (#1448)Adam Izraelevitz
Added prefixing and a compiler plugin to improve naming. Only works for Scala 2.12 and above. Co-authored-by: Jack Koenig <koenig@sifive.com>
2020-07-22Basic model checking API (#1499)Tom Alcorn
* Add `check(...)` affordance * Add assert (renamed from check and fixed) * Add verification statements * Move formal to experimental.verification * Make test use ChiselStage `generateFirrtl` has been cut from Chisel * Fix newly introduced style warnings * Fix some old style warnings for good measure * Revert "Fix some old style warnings for good measure" This reverts commit 31d51726c2faa4c277230104bd469ff7ffefc890. * Cut scalastyle comments * Cut formal delimiter comments
2020-07-21Delete outdated scalastyle configuration comments from sourceAlbert Magyar
2020-07-13Provide an implementation of litOption() for BundleLits (#1280)Jim Lawson
2020-06-29- A few final fixes after the rebasechick
2020-06-29This adds a mechanism for the unittests to be run with the TreadleBackendchick
This mechanism is not enabled and should not change the behavior of existing tests A following PR will deliver a switch that will allow changing the backend. The reasons for this PR - Treadle tests run much faster, enabling quicker debugging and CI cycles - This will help ensure fidelity of Treadle to the Verilator backend A few tests are marked as verilator only due to black box limitations Change treadle to a direct dependency I tried to make it a test only dependency but the TesterDriver sits in src/main requiring that regular compile have access to treadle Oops, made treadle the default A number of changes in response to @ducky64 review - made backend check clearer and add error handling for multiple backends specified - Fixed duplicate TargetDirAnnotation uses in Treadle backend - Cleaned up BlackBox test formatting - Undid unnecessary debugging changes from Counter - Undid .gitignore change, that should be on another PR A number of changes in response to @ducky64 review - Undid debugging changes made to BitWiseOps
2020-06-23Don't run FIRRTL in FlattenSpec's ChiselStage (#1493)Schuyler Eldridge
Fix a bug in FlattenSpec where ChiselStage was running the FIRRTL compiler in ChiselStage and then re-running the FIRRTL compiler. This changes it to be like InlineSpec and to not run FIRRTL during ChiselStage. This was manually backported to 3.3.x. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-06-22Clarify chiselTests.Utils.extractCause ScaladocSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-06-22Remove Driver usage in ChiselSpecSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-06-22Use ChiselStage in TestsSchuyler Eldridge
This migrates the tests to Chisel 3.4/FIRRTL 1.4. This primarily involves removing usages of deprecated methods including: - Remove usages of Driver - Use ChiselStage methods instead of BackendCompilationUtilities methods - Use Dependency API for custom transforms - Use extractCause to unpack StackError Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-06-22Add containsCause exception search testing utilSchuyler Eldridge
Adds a new method, chiselTests.Util.containsCause, that will search for a polymorphic exception anywhere in a stack trace. This is useful if exceptions may move around (e.g., if they are suddenly wrapped in a StageError). Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-06-22Canonicalize construction of Decoupled with no payload (#785)Jack Koenig
* Canonicalize construction of empty Decoupled * Change signature after dev meeting discussion * Make EmptyBundle private and final * Add test case for Decoupled with no payload * Apply suggestions from code review Co-authored-by: Richard Lin <richard.lin@berkeley.edu> Co-authored-by: Albert Magyar <albert.magyar@gmail.com> Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: Adam Izraelevitz <azidar@gmail.com> Co-authored-by: Richard Lin <richard.lin@berkeley.edu> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-06-16Move Deprecated LFSR16 to CompatibilitySchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-06-08Report Builder.error errors as exceptions outside hardware context (#1425)Albert Magyar
* Immediately throw Builder.error errors outside hardware context * Add example of hidden no-hardware-context error from #1422 Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-06-08Grouping Chisel API (#1073)Adam Izraelevitz
* Added group chisel API * Removed println * Added scaladoc * Added more tests * Cleaned spacing and removed println Co-authored-by: Chick Markley <chick@qrhino.com> Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu> Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-05-06Test that Elaborate only runs onceSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-05-05Update scalatest 3.1.1 (#1430)Jim Lawson
* Update scalatest to 3.1.1 * Update scalatest to 3.1.1 * Update scalatest to 3.1.1 * Add missing org.scalatest.flatspec.AnyFlatSpec import. Co-authored-by: Scala Steward <me@scala-steward.org> Co-authored-by: Scala Steward <43047562+scala-steward@users.noreply.github.com>
2020-04-16Add tests for async reset regs of non-UInt types (#1414)Jack Koenig
2020-04-13Update scalatest to 3.1.0 (#1394)Jim Lawson
Co-authored-by: Scala Steward <me@scala-steward.org>
2020-04-10Expose checkTypeEquivalence as a public API (#1402)Sequencer
2020-04-06enable Lit for Record. (#1400)Sequencer
2020-03-24Propagate user compile options for Chisel.Module (#1387)Jack Koenig
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-03-24Add ChiselStageSpec for string/circuit emissionSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-03-23Add NoChiselNamePrefix to ignore instances in @chiselName (#1383)Jack Koenig
Add trait chisel3.experimental.NoChiselNamePrefix which causes @chiselName to skip naming of the instance effectively preventing it from prefixing any vals inside the instance. It can be applied to classes such that all instances of that class have this property, or to individual instances (via creating an anonymous class inline). Also add basic ScalaDoc for NoChiselNamePrefix and chiselName.
2020-03-19Test nested ChiselException in ChiselMainSchuyler Eldridge
Adds two tests: 1. Test that an internal requirement failure (a bare exception) inside a Builder is properly reported/trimmed by ChsielStage/ChiselMain 2. Test that the full stack trace includes the ChiselException Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-03-11Wrap elaboration in ChiselExceptionSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> squash! Wrap elaboration in ChiselException
2020-03-06Provide API to set concrete type of implicit reset (#1361)Jack Koenig
Introduces mutually-exclusive traits RequireAsyncReset and RequireSyncReset to set the type of the implicit reset in MultiIOModules. The Scala-type remains Reset, but the Chisel elaboration-time checks apply. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-03-02Cleanup aspects (#1359)Adam Izraelevitz
* Clean up aspects * Refactored InjectingAspect with InjectorAspect * Made AspectLibrary work with objects * Cleaned up code * Apply suggestions from code review * Added tests, removed deprecated newInstance call * Backed out removal of newInstance as exceptions were different * Removed trailing commas
2020-02-12Fix := of Reset and AsyncReset to DontCare (#1336)Jack Koenig
2020-02-10Make Queue.irrevocable work properly in chisel3Edward Wang
Close #1134
2020-02-10Printf: Add support for tabs, and give helpful error messages (#1323) (#1326)Jack Koenig
Co-authored-by: Megan Wachs <megan@sifive.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-02-06Emit FIRRTL andr, orr for Bits.{andR, orR}Schuyler Eldridge
Change the emission strategy for Bits methods andR and orR to emit FIRRTL bitwise reduce operations andr and orr. Add two tests that assert the correct behavior of these operations in BitwiseOpsSpec. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-03Add read-under-write parameter to SyncReadMem (#1183)Albert Magyar
* Add support for readUnderWrite to SyncReadMem * Add write collision behavior test to MemorySpec * Update constant names
2020-01-31Merge branch 'master' into add-asbool-to-clockChick Markley
2020-01-21Merge branch 'master' into big-decimal-methods-for-num-typeschick
# Conflicts: # src/test/scala/chiselTests/IntervalSpec.scala
2020-01-21Merge branch 'master' into add-asbool-to-clockJim Lawson
generated by cgit v1.2.3 (git 2.25.1) at 2026-02-01 19:17:41 +0000