summaryrefslogtreecommitdiff
path: root/src/test/scala
AgeCommit message (Collapse)Author
2019-05-22Add chisel.stage.phases.AddImplicitOutputFileSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-22Add chisel3.stage.phases.Emitter PhaseSchuyler Eldridge
This adds an Emitter Phase that writes a ChiselCircuitAnnotation to a file if a ChiselOutputFileAnnotation is present. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-22Add chisel3.stage.phases.Convert PhaseSchuyler Eldridge
This coalesces three distinct operations into one Convert Phase: 1. Chisel Circuit to FIRRTL Circuit (CHIRRTL) conversion 2. Conversion of Chisel Annotations to FIRRTL Annotations 3. Generation of RunFirrtlTransformAnnotations Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-Authored-By: chick <chick@qrhino.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-22Add chisel3.stage.phases.Elaborate PhaseSchuyler Eldridge
This adds an Elaborate Phase that expands ChiselGeneratorAnnotations into ChiselCircuitAnnotations and deletes the original. Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-Authored-By: chick <chick@qrhino.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-22Add chisel3.stage.phases.Checks PhaseSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-22Add ChiselOptionsViewSchuyler Eldridge
Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-Authored-By: chick <chick@qrhino.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-22Add chisel3.stage AnnotationsSchuyler Eldridge
This adds the following FIRRTL Annotations to Chisel: - NoRunFirrtlCompilerAnnotation - PrintFullStackTraceAnnotation - ChiselGeneratorAnnotation - ChiselCircuitAnnotation - ChiselOutputFileAnnotation This includes tests for ChiselGeneratorAnnotation as this Annotation is able to be constructed from a String and to elaborate itself. Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-Authored-By: chick <chick@qrhino.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-20Repackagecore rebase (#1078)Jim Lawson
* Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3 and deal with the subsequent fallout. * Move Aggregate, Clock, Mem, Printf, Reg * Move almost all chisel3.core definitions to chisel3 or chisel3.experimental * Revive core package object to provide aliases for moved definitions. * Cleanup package definitions; eliminate ambiguous implicits * Move more definitions to experimental. Extract BaseModule, DataMirror, ExtModule, IO into their own files. * Put BitPat back in chisel3.util * More experimental motion - avoid multiple import definitions. * Add experimental.FixedPoint alias * Add EnumType definition to core package. Update deprecated messages to refer to correct object * Move FixedPoint into the experimental package (but keep it in Bits.scala). * Add missing implicits to core/package - compatibility * Cleanup: update ScalaDoc references; remove unused imports * Add Reset alias to core/package * Use common 3.2 version in deprecation warning * Move Binding from core to internal. * Optimize imports. * Repair IntelliJ's overly cleanliness. * Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3 and deal with the subsequent fallout. Move Aggregate, Clock, Mem, Printf, Reg Move almost all chisel3.core definitions to chisel3 or chisel3.experimental Revive core package object to provide aliases for moved definitions. Cleanup package definitions; eliminate ambiguous implicits Move more definitions to experimental. Extract BaseModule, DataMirror, ExtModule, IO into their own files. Add EnumType definition to core package. Update deprecated messages to refer to correct object Move FixedPoint into the experimental package (but keep it in Bits.scala). Add missing implicits to core/package - compatibility Cleanup: update ScalaDoc references; remove unused imports Use common 3.2 version in deprecation warning Move Binding from core to internal. * Change == to reference equality (eq) in Data print (#1044) * Remove @chiselName from MixedVec (#1045) * Fix enum annotations (#936) * Turned off strong enum annotations because they weren't working with Vec indexes * Add new EnumVecAnnotation for vecs of enums and vecs of bundles with enum fields * Changed Clock's width parameter back to a fixed constant value of 1 * Fixed enum annotations for Vecs of Bundles which contain enum elements * Fixed usage of "when/otherwise" to use consistent style * Add Record to type hierarchy documentation * Undeprecate isLit (#1048) * move doNotDedup to experimental (#1008) * Aggregate coverage - aggregate tests but not publishing (#1040) Discover a working combination of aggregate usage to enable coverage of subproject testing but publish a single Jar. Use "scalastyle-test-config.xml" for scalastyle config in tests. Enable "_" in method names and accept method names ending in "_=". Re-sync scalastyle-test-config.xml with scalastyle-config.xml This should finally fix #772. * Check field referential equality in autoclonetype (#1047) * Allow naming annotation to work outside builder context (#1051) * Try to eliminate JVM hang due to static initialization deadlock (#1053) * Make core.DontCare private to chisel3 (#1054) Force clients to access 'DontCare' through the chisel3 package to ensure it's created as a chisel3 object and not a client object. * Ignore empty aggregates elements when binding aggregate direction (#946) Previously, including an empty aggregate in a Bundle would cause a MixedDirectionAggregateException because it has no elements and thus doesn't have a direction * Add SampleElementBinding for Vec sample elements * Add ActualDirection.Empty for bound empty aggregates * Detect bundle aliasing (#1050) * Implement connectFromBits in ChiselEnum (#1052) This is necessary to use ChiselEnum in aggregates where things are casted using .asTypeOf * Optimize imports. * Move Analog to experimental. * More repackage cleanup - reduce differences with master. * Cleanup chisel3 references. * More chisel3 reference cleanup. * Merge cleanup. * Remove unused import * Bump core deprecation to 3.3 * Move DontCare back into Data.scala inside package internal * Re-indent experimental/internal package code * Move code back to original files - facilitate comparison with other branches * Some code motion, update imports, minimize master differences Move exceptions up to chisel3 package object - they're part of the interface. * More master diff minimization. * Try to eliminate JVM hang due to static initialization deadlock (#1053) * Ignore empty aggregates elements when binding aggregate direction (#946) Previously, including an empty aggregate in a Bundle would cause a MixedDirectionAggregateException because it has no elements and thus doesn't have a direction * Add SampleElementBinding for Vec sample elements * Add ActualDirection.Empty for bound empty aggregates * Implement connectFromBits in ChiselEnum (#1052) This is necessary to use ChiselEnum in aggregates where things are casted using .asTypeOf * Move Analog to experimental. More repackage cleanup - reduce differences with master. Cleanup chisel3 references. More chisel3 reference cleanup. * Fix wrong directionality for Vec(Flipped()) Create Chisel IR Port() in a way that Converter is happy with. Also add more extensive test suite for future-proofing. Close #1063 * Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3 and deal with the subsequent fallout. Move Aggregate, Clock, Mem, Printf, Reg Move almost all chisel3.core definitions to chisel3 or chisel3.experimental Revive core package object to provide aliases for moved definitions. Cleanup package definitions; eliminate ambiguous implicits Move more definitions to experimental. Extract BaseModule, DataMirror, ExtModule, IO into their own files. Put BitPat back in chisel3.util More experimental motion - avoid multiple import definitions. Add experimental.FixedPoint alias Add EnumType definition to core package. Update deprecated messages to refer to correct object Move FixedPoint into the experimental package (but keep it in Bits.scala). Add missing implicits to core/package - compatibility Cleanup: update ScalaDoc references; remove unused imports Add Reset alias to core/package Use common 3.2 version in deprecation warning Move Binding from core to internal. Optimize imports. Repair IntelliJ's overly cleanliness. Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3 and deal with the subsequent fallout. Move Aggregate, Clock, Mem, Printf, Reg Move almost all chisel3.core definitions to chisel3 or chisel3.experimental Revive core package object to provide aliases for moved definitions. Cleanup package definitions; eliminate ambiguous implicits Move more definitions to experimental. Extract BaseModule, DataMirror, ExtModule, IO into their own files. Add EnumType definition to core package. Update deprecated messages to refer to correct object Move FixedPoint into the experimental package (but keep it in Bits.scala). Add missing implicits to core/package - compatibility Cleanup: update ScalaDoc references; remove unused imports Use common 3.2 version in deprecation warning Move Binding from core to internal. Optimize imports. Merge cleanup. Remove unused import Bump core deprecation to 3.3 Move DontCare back into Data.scala inside package internal Re-indent experimental/internal package code Move code back to original files - facilitate comparison with other branches Some code motion, update imports, minimize master differences Move exceptions up to chisel3 package object - they're part of the interface. More master diff minimization. Fix minor discrepancies with repackagecore-testbed * Remove redundant imports As part of its import updating process, IntelliJ converted some import statements to `import package.{object, _}`. Is this intended to show an explicit dependency on `package.object` and a further dependency on `package` implicits? Unsure. Replace these with `import package._` * Move the BaseModule object into the internal package.
2019-05-13RawModule with no reset should be able to use withClock method. (#1065)Chick Markley
* RawModule with no reset should be able to use withClock method. - refactor ClockAndReset - now has `clockOpt: Option[Clock]` and `resetOpt: Option[Reset]` constructor params - convenience methods clock and reset tries to deref the option - ClockAndReset.empty is factory method for (None, None) - In Builder - forcedClock does not check resetOpt now - forcedReset does not check clockOpt now - withClock no longer looks at resetOpt - withReset no longer looks at clockOpt - Module starts with empty ClockAndReset * RawModule with no reset should be able to use withClock method. Refactor again based on @ducky64 comments - refactor away ClockAndReset, now builder just has a - currentClock - currentReset - withClock, withRest, withClockAndReset just use these fields directly * RawModule with no reset should be able to use withClock method. - Fixed typo in withReset handler, now picks up new reset
2019-05-10Augment LFSR16 test to test the enable as wellAndrew Waterman
2019-05-09PRNG state UInt->Vec[Bool], make async reset safeSchuyler Eldridge
Changes the internal state of PRNG to use Vec[Bool] instead of UInt. This fixes an @aswaterman identified future problem with asynchronous reset. A register with an asynchronous reset can only be reset to a literal. Previously, an LFSR would store state as a UInt. If it was not parameterized with a seed it should have its least significant bit reset to something to avoid locking up. It's ideal to not reset the full UInt (better test coverage, decreased reset fanout). However, it's difficult to only reset one bit of a UInt. Conversely, it's trivial to reset one bit of a Vec[Bool]. This also moves PRNG/LFSR closer to a canonical representation of their internal state, i.e., it's natural to think of generalizing Vec[Bool] to arbitrary finite fields (Vec[A <: Field]) whereas UInt is tightly coupled to GF2. Minor updates: - Updates/fixes to some scaladoc - Add assertion to period test to make sure LFSR is changing Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-09Fix treatment of Vec of Analog and Vec of Bundle of Analog (#1091)Jack Koenig
* IO(Analog) fixed for RawModule * Add a Analog Port for RawModule test & spec * Fixes around Module instantiation and ports in AnalogPortRawModuleTest * Shorten Comment * Add Data.isSynthesizable to distinguish SampleElementBinding This helps clarify the notion of being bound but not hardware. Data.topBindingOpt is now used to get the *actual* top binding, including across SampleElements (eg. in Analog checking that the top is bound to a Port or a Wire) * Fix pretty printing for Vec * Refactor tests for Vec of Analog, add test for Vec of Bundle of Analog
2019-05-09Deprecate LFSR16, use FibonacciLFSR internallySchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-09Add Lfsr testsSchuyler Eldridge
Add LFSR tests using LFSR16 testing infrastructure. This also adds tests that are the same as the examples shown for LFSR scaladoc. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-09Add chisel3.util.random lib w/ LFSR generatorSchuyler Eldridge
Builds out PRNG and LFSR type hierarchy. PRNG is the base class of LFSR of which Galois and Fibonacci are concrete implementations. PRNGs contain state (a UInt) and an update (delta) function. They have a compile-time optional seed to set the PRNG state. The seed/state can also be set at run-time. PRNGs can be run-time parameterized based on how many updates they should do per cycle and whether or not to send the seed through step-count state updates before loading it. (h/t @jwright6323) LFSRs are parameterized in a reduction operation (XOR or XNOR). An LFSR that does NOT have a seed will be automatically initialized to a minimally safe state (set/reset one bit) based on their reduction operation. (h/t @aswaterman) Adds Galois and Fibonacci LFSRs that define appropriate update functions. Companion objects provide helpers to automatically generate maximal period variants. Taps are provide for a very large set of widths. The LFSR companion object provides an apply method to generate a Fibonacci LFSR random variable (like the old LFSR16).
2019-05-08Genericize LFSR testing infrastructureSchuyler Eldridge
Make LFSR testing generic to enable it to test other LFSRs. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-01Make asTypeOf work for bundles with zero-width fields. (#1079)Paul Rigge
Closes #1075.
2019-04-26Bundle literals implementation (#1057)Richard Lin
2019-04-24Add back Int forms of Mem do_apply methods (#1082)Jack Koenig
This is necessary to support code that imports an implicit conversion from Int to UInt
2019-04-23Change size of memories from Int to BigInt (#1076)Jack Koenig
2019-04-19Fix wrong directionality for Vec(Flipped())Edward Wang
Create Chisel IR Port() in a way that Converter is happy with. Also add more extensive test suite for future-proofing. Close #1063
2019-04-12Implement connectFromBits in ChiselEnum (#1052)Jack Koenig
This is necessary to use ChiselEnum in aggregates where things are casted using .asTypeOf
2019-04-01Detect bundle aliasing (#1050)Richard Lin
2019-03-29Ignore empty aggregates elements when binding aggregate direction (#946)Jack Koenig
Previously, including an empty aggregate in a Bundle would cause a MixedDirectionAggregateException because it has no elements and thus doesn't have a direction * Add SampleElementBinding for Vec sample elements * Add ActualDirection.Empty for bound empty aggregates
2019-03-25Allow naming annotation to work outside builder context (#1051)Richard Lin
2019-03-25Check field referential equality in autoclonetype (#1047)Richard Lin
2019-03-23move doNotDedup to experimental (#1008)Sequencer
2019-03-22Fix enum annotations (#936)Hasan Genc
* Turned off strong enum annotations because they weren't working with Vec indexes * Add new EnumVecAnnotation for vecs of enums and vecs of bundles with enum fields * Changed Clock's width parameter back to a fixed constant value of 1 * Fixed enum annotations for Vecs of Bundles which contain enum elements * Fixed usage of "when/otherwise" to use consistent style
2019-03-18Split #974 into two PRs - scalastyle updates (#1037)Jim Lawson
* Update style warnings now that subprojects are aggregated. Use "scalastyle-test-config.xml" for scalastyle config in tests. Enable "_" in method names and accept method names ending in "_=". Re-sync scalastyle-test-config.xml with scalastyle-config.xml * Remove bogus tests that crept in with git add * Add missing import.
2019-03-15Add width constraint to PopCount test (which currently fails)Andrew Waterman
2019-03-15Add PopCount testAndrew Waterman
2019-02-19Add HasBlackBoxPath to BlackBoxUtils.scala (#903)Albert Chen
* Add HasBlackBoxPath trait * Use 'setResource' instead of 'addResource' * Add ScalaDoc
2019-02-19Add TransitNameSpecSchuyler Eldridge
This adds a test of chisel3.util.TransitName (which is used for the TransitName documentation). Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-02-19Mainline Chisel multi-clock functionality (#1013)edwardcwang
Close #1009
2019-02-19Util doc lsfr (#1021)Chick Markley
* Update documentation for LSFR16 - Moved bulk of comments to object. - Added an example - Added functional test - example based on section of test * Update documentation for LSFR16 - Moved bulk of comments to object. - Added an example - Added functional test - example based on section of test * Update documentation for LSFR16 - Fixed typos in LFSR - Reduce trials a little - Add test of LFSR period * Update documentation for LSFR16 - Fixed remaining LSFR, arrgh - Removed intellij specific warning suppressor - Fixed comments/scaladoc wording and case. * Update documentation for LSFR16 - Use printable interpolator as example of printing out a Vec
2019-02-01Queue TestsBrendan Sweeney
2019-01-25WireDefault instead of WireInit, keep WireInit around (#986)Martin Schoeberl
2019-01-22Define Data .toString (#985)Richard Lin
toString on Data subtypes will now print the type and optionally binding information including literals and IO names as feasible.
2019-01-22Fix BoringUtilsSpec to require no dedupSchuyler Eldridge
This adds two tests to the BoringUtilsSpec to explicitly verify that deduplication is required when boring. This adds tests that both verify that the test passes as expected with deduplication enabled and that the same test fails with deduplication disabled. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-01-22Add Rocket Chip-style clonemodule as CloneModuleAsRecord to experimental (#943)Albert Magyar
2019-01-21Support DontCare in Mux and cloneSupertype (#995)Richard Lin
2019-01-11Add test for chiselNaming of Seq[Data]Andrew Waterman
2018-12-19Fix width inferencing issue (#952)Jack Koenig
* Fix width propagation of non-literals in WireInit and RegInit * Change .getWidth to throw an exception instead of calling .get * Add utilities for checking inferred vs. known widths * Add tests for Wire, WireInit, Reg, and RegInit width inference * Add ScalaDoc for Reg, Wire, RegInit, and WireInit
2018-12-04Add asBool, deprecate toBoolJack Koenig
2018-12-04Add asBools, deprecate toBoolsJack Koenig
2018-12-04Make toBools support chained applyJack Koenig
The expanded version substituted in by the macro was misspelled, renamed from toBools -> do_toBools as expected by the macro
2018-11-26Trim Stack Trace (#931)Albert Chen
- Trim stack trace to show better, reduced information to the user - Add --full-stacktrace to FIRRTL option to show full stack trace
2018-11-20Make Vec cloneType keep directions of elements (#945)Jack Koenig
Fixes #893
2018-11-01Add BigInt / Int to Bool conversion (0.B, 1.B) (#913)Richard Lin
2018-10-29Turn off strong enum annotations (#916)Hasan Genc
* Turned off strong enum annotations because they weren't working with Vec indexes * Ignore annotation tests using ScalaTest's 'ignore', rather than by commenting them out
generated by cgit v1.2.3 (git 2.25.1) at 2026-02-01 11:31:19 +0000