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2023-01-12TruthTable improvements: structural equality and delete sort (backport ↵mergify[bot]
#2935) (#2936) * TruthTable improvements: structural equality and delete sort (#2935) We had implemented equals, but not hashCode. This commit also changes the implemental of equals to just use the underlying values instead of wasting the compute calling .toString. Delete TruthTable.sort, it is unused. (cherry picked from commit b5d9c08b2d0994b94df2380425282206fe1f25bc) * Restore and deprecate TruthTable.sort Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2023-01-11Promote ChiselEnum user APIs from experimental (backport #2929) (#2931)mergify[bot]
* Promote ChiselEnum user APIs from experimental (#2929) They are commonly used and if we were ever to change them, we will need to go through a deprecation process anyway. Note that the EnumAnnotations remain in chisel3.experimental because, like all Chisel annotation support, they are slated to be deprecated and removed. (cherry picked from commit 424e9446f1675fe0168e22bdfbbe85db997376e6) # Conflicts: # docs/src/cookbooks/verilog-vs-chisel.md # docs/src/explanations/chisel-enum.md * Maintain binary compatbility, use aliases in chisel3 package * Deprecate the actual classes in chisel3.experimental * Also fix backport conflicts Co-authored-by: Jack Koenig <koenig@sifive.com>
2023-01-10Check for Vec subaccess in NamedComponent and throw a nicer error. (backport ↵mergify[bot]
#2907) (#2928) * Check for Vec subaccess in NamedComponent and throw a nicer error. (#2907) This would previously end up throwing an exception later, when trying to create a component name and realizing that it was invalid. Instead, this detects Vec subaccesses early, and gives a more precise error and suggestion. (cherry picked from commit d8c30961c7b293ee19024a487698630367ee71c6) # Conflicts: # core/src/main/scala/chisel3/internal/Builder.scala * Resolve backport conflicts Co-authored-by: Mike Urbach <mikeurbach@gmail.com>
2022-12-24FlatIOSpec: make sure the Analog test is using FLatIO (#2909) (#2910)mergify[bot]
(cherry picked from commit b91a2050aeb143aa80762dfb1b40f1e5035de4b5) Co-authored-by: Megan Wachs <megan@sifive.com>
2022-12-10Fix string interpolation in `util.exprimental.decode.bitset` (#2882) (#2883)mergify[bot]
* Fix BitSet decoder API when errorBit=False When errorBit is set to False, the original code will return `Unit` which will be `()` in interpolated string. * Add testcases for both errorBit cases in BitSetSpec (cherry picked from commit 42416cb6c6a3019fc29b9d98cfea3e3bb4e42684) Co-authored-by: Ocean Shen <30361859+OceanS2000@users.noreply.github.com>
2022-12-07Make PriorityMux stack safe (backport #2854) (#2855)mergify[bot]
* Make PriorityMux stack safe (#2854) It used to be implemented with recursion, now it's implemented with a stack safe reverse and foldLeft. Also there were no tests for PriorityMux so I added one which helps prove the change is functionally correct. (cherry picked from commit 269ce472e9aa0c242fc028871a1fd5b045c82f83) # Conflicts: # src/test/scala/chiselTests/util/PipeSpec.scala * Resolve backport conflicts Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2022-11-15fullModulePorts + Opaque Types Fix and Test (#2845) (#2846)mergify[bot]
(cherry picked from commit 49feb083c69066988ca0666ea4249a86570e2589) Co-authored-by: Megan Wachs <megan@sifive.com>
2022-11-10Update CompatibilityInteroperabilitySpec.scala (#2840) (#2842)mergify[bot]
(cherry picked from commit aa596b98d5e030294041f2e90eee1f78ca1e401b) Co-authored-by: Megan Wachs <megan@sifive.com>
2022-11-10 Warn on S-interpolator usage for assert, assume and printf (backport #2751) ↵Aditya Naik
(#2757) * Add internal methods to maintain binary compatibility Co-authored-by: Megan Wachs <megan@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-11-10Add unit tests and fix for #2794 , add unit tests for #2773 (backport ↵mergify[bot]
#2792) (#2834) * Fixup and unit tests for D/I of IOs without explicit Input/Output (#2792) (cherry picked from commit f24a624863f0fc460fd862238688ea8612ffdf5e) # Conflicts: # core/src/main/scala/chisel3/Module.scala * Resolve backport conflicts Co-authored-by: Megan Wachs <megan@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-11-10Unify Chisel2 and chisel3 directionality (backport #2634) (#2837)mergify[bot]
* Unify Chisel2 and chisel3 directionality (#2634) Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit 1aea4ef96466cbe08150d20c85c88b81e4e4f80f) # Conflicts: # core/src/main/scala/chisel3/Aggregate.scala # core/src/main/scala/chisel3/Module.scala # src/test/scala/chiselTests/Direction.scala * fix up backport * fix up backport * clean up diff * make test order like it was on master Co-authored-by: Adam Izraelevitz <adam.izraelevitz@sifive.com> Co-authored-by: Megan Wachs <megan@sifive.com>
2022-11-08Switch to using experimental trait for OpaqueTypes (backport #2783) (#2836)mergify[bot]
* Switch to using experimental trait for OpaqueTypes (#2783) This makes it more clear that the feature is experimental. Users may still override the opaqueType method for more dynamic control over when instances of a given Record are OpaqueTypes or not, but they are discouraged from doing so. (cherry picked from commit 7525dc71ccc2050d8e4a68b38f3b76920ba693fc) * Fix cloneType in RecordSpec Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-11-08Improve Record.bind and Detect Records with unstable elements (backport ↵mergify[bot]
#2829) (#2831) * Add Aggregate.elementsIterator and micro-optimize elementsIterator provides a more efficient API for iterating on the elements of Aggregates. It is especially useful for Records where getElements returns a Seq and thus eagerly constructs a new datastructure which may then just be iterated on anyway. This new elementsIterator API is then used throughout the codebase where it makes sense. Also change Vec.getElements to just return the underlying self instead of constructing a new Seq. (cherry picked from commit defa440b349031475daeff4024fad04925cccee6) # Conflicts: # core/src/main/scala/chisel3/Aggregate.scala # core/src/main/scala/chisel3/Module.scala # core/src/main/scala/chisel3/experimental/Trace.scala * Move Aggregate.bind inline into Record.bind Vec overrides bind and does not call the version in Aggregate so the version in Aggregate is misleading in that its only ever used by Records. Now there is no version in Aggregate and the actual functionality and use is more clear. (cherry picked from commit b054c30ba47026cb2a9b28c696a0a0a58b1e2ee7) # Conflicts: # core/src/main/scala/chisel3/Aggregate.scala * Extract and optimize duplicate checking Record.bind This replaces an immutable.Map with a single mutable.HashSet and saves the allocation of # elements Seqs. (cherry picked from commit 832ea52bc23424bb75b9654422b725a9cafaef40) # Conflicts: # core/src/main/scala/chisel3/Aggregate.scala * Add check for Records that define def elements (cherry picked from commit a4f223415de19e2a732e0b6a8fe681f706a19a56) * Resolve backport conflicts * Make elementsIterator final and package private * Waive false MiMa failure Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-11-07Bugfix converter clearing flips (backport #2788) (#2832)mergify[bot]
* Bugfix converter clearing flips (#2788) * Bugfix: Output on Vec of bundle with mixed field orientations * Bugfix OpaqueTypes clearing flips (cherry picked from commit f05bff1a337589bafebd08783bb0f6a72092a95a) # Conflicts: # src/test/scala/chiselTests/Direction.scala * Resolve backport conflicts Co-authored-by: Adam Izraelevitz <adam.izraelevitz@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2022-11-07Add DataMirror.getParent for getting parents of Modules (#2825) (#2833)mergify[bot]
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit fce8394bb0ddc9ae0d9c6668e034e483bd6b71c5) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-11-05Support Analog in DataView (#2782) (#2828)mergify[bot]
Co-authored-by: Megan Wachs <megan@sifive.com> (cherry picked from commit 26100a875c69bf56f7442fac82ca9c74ad3596eb) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-11-04Add PartialDataView.supertype (backport #2826) (#2827)mergify[bot]
* Add PartialDataView.supertype (#2826) This factory method makes it easy to create PartialDataViews from a Bundle type to its supertype. Because of the typing relationship, there is no need to provide a mapping between fields. The only thing necessary is to provide a function for constructing an instance of the supertype from an instance of the subtype. (cherry picked from commit 251d454a224e5a961438ba0ea41134d7da7a5992) # Conflicts: # core/src/main/scala/chisel3/experimental/dataview/package.scala # src/test/scala/chiselTests/experimental/DataView.scala * Resolve backport conflicts Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-10-23Fix for <> to BlackBox.IO with Compatibility Bundles (#2801) (#2803)mergify[bot]
MonoConnect.traceFlow now properly handles coerced directions. Also minor improvement to getClassName especially useful in test case printf debugging. (cherry picked from commit 3aba755bdcf996c0fbd846d13268fd6641b29e96) Co-authored-by: Megan Wachs <megan@sifive.com>
2022-10-23Don't invalidate ExtModule ports in an explicitInvalidate = true context ↵mergify[bot]
(backport #2795) (#2799) * Don't invalidate ExtModule ports in an explicitInvalidate = true context (#2795) * Don't invalidate ExtModule ports in an explicitInvalidate = true context ExtModule ports were previously invalidated in the emitted FIRRTL, which is correct in a NonStrict / `Chisel._` compatibility context but not in newer chisel3 code where `explicitInvalidate = true`. (cherry picked from commit 8e24a281545d25f6501dcc872eabdfb30bacd69d) # Conflicts: # core/src/main/scala/chisel3/BlackBox.scala * Resolve backport conflicts Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-10-19Don't modify the Builder prefix if reinvoking suggestName on a Data ↵mergify[bot]
(backport #2789) (#2790) * Only set the chisel3 Builder prefix during the first invocation of suggestName (cherry picked from commit b684506abab2f7b99d56181d548cb8119d317323) # Conflicts: # core/src/main/scala/chisel3/internal/Builder.scala * Add simple test to show bug fix (cherry picked from commit 255068b105de77a045a0016e3a157b52a81c86d6) * Fix merge conflict * Fix test to not use Hardware inside a bundle for prefixing Co-authored-by: Jared Barocsi <jared.barocsi@sifive.com>
2022-10-17Add opt-in AutoCloneType for Records (backport #2781) (#2785)mergify[bot]
* Add opt-in AutoCloneType for Records (#2781) There is a new trait, chisel3.experimental.AutoCloneType that is mixed in to Bundle and can optionally be mixed in to user-defined Records. The compiler plugin prints a deprecation warning on any user-defined implementation of cloneType, telling the user to mix in AutoCloneType before upgrading to 3.6. (cherry picked from commit a234fd48ac8f5942c38fef5797292014e407b586) # Conflicts: # core/src/main/scala/chisel3/Aggregate.scala # plugin/src/main/scala/chisel3/internal/plugin/BundleComponent.scala * Resolve backport conflicts * Do not make MixedVec extend AutoCloneType It is a binary incompatible change that can wait for 3.6. * Waive MiMa false positives Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-10-10Replace execution test with CHIRRTL match test (#2769) (#2770)mergify[bot]
(cherry picked from commit 693678dbea0cc4b92a8d8de690768fdc7d90fd14) Co-authored-by: Aditya Naik <91489422+adkian-sifive@users.noreply.github.com>
2022-10-07Make nested IsInstantiables with Data in them work (#2761) (#2766)mergify[bot]
* Add unit test for Issue 2760 * checkpoint: Fix for nested instance * remove comments about stuff not working * make the test check the output a little more * relax the requirement on returning empty ioMap * Update core/src/main/scala/chisel3/experimental/hierarchy/core/Lookupable.scala * Update core/src/main/scala/chisel3/Data.scala * Update core/src/main/scala/chisel3/experimental/hierarchy/core/Lookupable.scala Co-authored-by: Jack Koenig <koenig@sifive.com> * Update src/test/scala/chiselTests/experimental/hierarchy/InstanceSpec.scala Co-authored-by: Jack Koenig <koenig@sifive.com> * Update core/src/main/scala/chisel3/experimental/hierarchy/core/Lookupable.scala * Add another unit test which unfortunately still passes * Update core/src/main/scala/chisel3/Data.scala * Update src/test/scala/chiselTests/experimental/hierarchy/InstanceSpec.scala Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit 1f9f26dc2bffcb4cc4daf2dc16c5cb455c6769ef) Co-authored-by: Megan Wachs <megan@sifive.com>
2022-10-06Update toPrintable for Enums (#2707) (#2763)mergify[bot]
(cherry picked from commit 0ff99ca8d573e3487ef496a21c95d962689c3cba) Co-authored-by: Aditya Naik <91489422+adkian-sifive@users.noreply.github.com>
2022-09-29Add lexical scope checks to Assert, Assume and Printf (#2706) (#2753)mergify[bot]
(cherry picked from commit f462c9f9307bebf3012da52432c3729cd752321c) Co-authored-by: Aditya Naik <91489422+adkian-sifive@users.noreply.github.com>
2022-09-27Use Treadle (on pull requests only) to speed up CI (backport #2341) (#2748)mergify[bot]
* Support using Treadle for 'sbt test' Treadle will be used as the "defaultBackend" when the environment variable CHISEL3_CI_USE_TREADLE is set. The intent is to set this variable during CI for pre-merge CI (aka on pull requests). (cherry picked from commit 7d39b7bd2b6f38dac90fe25064744ffc0ada0fe4) * Use Treadle for CI on pull requests (cherry picked from commit 82660673e56a816e68fcc068e3e04e127f076faf) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-09-01Remove incorrect clock warning on Mem.read (backport #2721) (#2722)mergify[bot]
* Remove incorrect clock warning on Mem.read (#2721) Mem.read is combinational and thus unaffected by the clock, and so it does not make sense to issue warnings about the current clock in this context. (cherry picked from commit 5fdf74f95e64cb69d6097547f20d789a83dbd735) * Keep old version of MemBase.clockWarning for binary compatibility This method is impossible for users to call, but it is easy enough to keep around a version of it to make MiMa happy. Co-authored-by: Andrew Waterman <andrew@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-08-31Wires should have source location information in firrtl (#2714) (#2716)mergify[bot]
- Remove line defeating having wire locators `implicit val noSourceInfo = UnlocatableSourceInfo` from `WireDefault#apply` - Add test to show locators (cherry picked from commit f701a9f8151891e3bf9019cd3229cb3f2cd1833b) Co-authored-by: Chick Markley <chick.markley@sifive.com>
2022-08-29Fix OpaqueSlot handling of contextual names (#2708) (#2712)mergify[bot]
We need to ensure that contextual names stay contextual (ie. sensitive to the module context which is important for naming ports). (cherry picked from commit cee255216c4a1bb658a2d8ddc03d966ce7ffb877) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-08-25Backport of eager error messages for annotations (3.5.x) (#2700) (#2705)Zachary Yedidia
2022-08-25Bugfix - OpaqueSlot replace invalid localName (backport #2701) (#2702)mergify[bot]
* Bugfix - OpaqueSlot replace invalid localName (#2701) (cherry picked from commit fb8ea2a2fac227f2570da992d7877de2eb1cf801) * Fix cloneTypes (#2703) Co-authored-by: Aditya Naik <91489422+adkian-sifive@users.noreply.github.com>
2022-08-24Backport .toTarget deprecation warning information (3.5.x) (#2697)Zachary Yedidia
2022-08-23Add AffectsChiselPrefix tests to PrefixSpec (#2693) (#2695)mergify[bot]
(cherry picked from commit 1a23b42429bf9de7dfab9f0a8e67334f8c5d4540) Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
2022-08-18Add generic `Data` equality (===) via extension method (#2669) (#2691)mergify[bot]
(cherry picked from commit 67cff8253740f19642006dba7eff58b1e5fa1291) Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
2022-08-16Add OpaqueType support to Records (backport #2662) (#2679)mergify[bot]
* Add OpaqueType support to Records (#2662) OpaqueTypes are essentially type aliases that hide the underlying type. They are implemented in Chisel as Records of a single, unnamed element where the wrapping Record does not exist in the emitted FIRRTL. Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit df5afee2d41b5bcd82d4013b977965c0dfe046fd) * Fix test compilation * Fix OpaqueType tests in RecordSpec Need to implement cloneType correctly and to warn instead of error when accessing .toTarget of non-hardware types because that is a warning (not error) in 3.5. * Waive MiMa false positives Co-authored-by: Aditya Naik <91489422+adkian-sifive@users.noreply.github.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-08-15Printables for verification preconditions (backport #2663) (#2680)mergify[bot]
* Printables for verification preconditions (#2663) Add support for printable within assert and assume verification statements Co-authored-by: Girish Pai <girish.pai@sifive.com> Co-authored-by: Megan Wachs <megan@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit 7df5653309b5e48e1732b335610d9a7e8449f903) * Waive MiMa false positive Co-authored-by: Aditya Naik <91489422+adkian-sifive@users.noreply.github.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-08-13Add option to treat warnings as errors (backport #2676) (#2677)mergify[bot]
* Add option to treat warnings as errors (#2676) Add --warnings-as-errors option (cherry picked from commit 498946663726955c380a1e420f5d7b9630000aad) # Conflicts: # core/src/main/scala/chisel3/experimental/hierarchy/Definition.scala # core/src/main/scala/chisel3/internal/Builder.scala # src/main/scala/chisel3/aop/injecting/InjectingAspect.scala # src/main/scala/chisel3/stage/ChiselOptions.scala # src/main/scala/chisel3/stage/package.scala # src/main/scala/chisel3/stage/phases/Elaborate.scala * Resolve backport conflicts Co-authored-by: Zachary Yedidia <zyedidia@gmail.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-08-12Show equivalent warnings/errors only once (#2673) (#2675)mergify[bot]
(cherry picked from commit ae76ff4cb303a6646e48dc044be47051b67e7cbb) Co-authored-by: Zachary Yedidia <zyedidia@gmail.com>
2022-08-12Add ability to suppress enum cast warnings (#2671) (#2674)mergify[bot]
(cherry picked from commit 1ad820f7f549eddcd7188b737f59a240e48a7f0a) Co-authored-by: Zachary Yedidia <zyedidia@gmail.com>
2022-07-28Implement DecoupledIO.map utility (#2646) (#2649)mergify[bot]
(cherry picked from commit b20df1d6cda03f6eef28ee480e0aade914c5face) Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
2022-07-21Deprecate chiselName and NoChiselNamePrefix trait (#2627) (#2633)mergify[bot]
Also remove all non-testing uses of chiselName. (cherry picked from commit 1c5d1b5317a0c9fe7ef9d15138065a817380a1e4) Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
2022-07-143.5x: Make explicit copy constructors for ExplicitCompileOptions (#2629)Megan Wachs
* Add copy constructors for compile options * Add tests for the copy constructors Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
2022-07-13New enhanced API for specifying Chisel to Firrtl Annotations (#2628) (#2631)mergify[bot]
(cherry picked from commit 4b10cf7a276e90b280c1fd57070566acac3d80d3) Co-authored-by: Girish Pai <girish.pai@sifive.com>
2022-07-08CompileOptions: add and use emitStrictConnects (#2622) (#2623)mergify[bot]
(cherry picked from commit 11e8cc60d6268301cff352b8a1d7c4d672b5be11) Co-authored-by: Megan Wachs <megan@sifive.com>
2022-07-06Refactor TruthTable.apply and add factory method for Espresso (backport ↵mergify[bot]
#2612) (#2620) * Refactor TruthTable.apply and add factory method for Espresso (#2612) Improves performance of creating TruthTables by processing entire BitPats rather than individual bits. New TruthTable factory method enables constructing TruthTables with semantics of OR-ing output BitPats together rather than erroring when multiple terms have the same input BitPat. This alternative factory method matches semantics for the output format of Espresso. Co-authored-by: Megan Wachs <megan@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit 231f14e74f112a9f721e774561126b2bd1250039) # Conflicts: # src/main/scala/chisel3/util/BitPat.scala * Resolve backport conflicts Co-authored-by: Aditya Naik <91489422+adkian-sifive@users.noreply.github.com>
2022-07-06Implement trait for Chisel compiler to name arbitrary non-Data types (#2610) ↵mergify[bot]
(#2617) Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: Megan Wachs <megan@sifive.com> (cherry picked from commit 3ab34cddd8b87c22d5fc31020f10ddb2f1990d51) Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
2022-06-23Add DataMirror isIO, isReg, isWire (#2601) (#2602)mergify[bot]
(cherry picked from commit 7fa0d8bf1cafcdf141046476a100abf021bdcac4) Co-authored-by: Zachary Yedidia <zyedidia@gmail.com>
2022-06-22Pass optional name in ImportDefinitionAnno (#2592) (#2594)mergify[bot]
Used for separate elaboration of Definition and Instance (cherry picked from commit 48d57cc8db6f38fdf0e23b7dce36caa404c871b8) Co-authored-by: Girish Pai <girish.pai@sifive.com>
2022-06-18Handle varargs constructor arguments in Bundle plugin (#2585) (#2588)mergify[bot]
Previously, the plugin would crash with a useless internal error. (cherry picked from commit 9fcfb252beb9f06d8d1409fe7db9c8b3b6b962ce) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-06-16Define leading '_' as API for creating temporaries (backport #2580) (#2581)mergify[bot]
* Define leading '_' as API for creating temporaries Chisel and FIRRTL have long used signals with names beginning with an underscore as an API to specify that the name does not really matter. Tools like Verilator follow a similar convention and exclude signals with underscore names from waveform dumps by default. With the introduction of compiler-plugin prefixing in Chisel 3.4, the convention remained but was hard for users to use unless the unnnamed signal existed outside of any prefix domain. Notably, unnamed signals are most useful when creating wires inside of utility methods which almost always results in the signal ending up with a prefix. With this commit, Chisel explicitly recognizes signals whos val names start with an underscore and preserve that underscore regardless of any prefixing. Chisel will also ignore such underscores when generating prefixes based on the temporary signal, preventing accidental double underscores in the names of signals that are prefixed by the temporary. (cherry picked from commit bd94366290886f3489d58f88b9768c7c11fa2cb6) * Remove unused defaultPrefix argument from _computeName (cherry picked from commit ec178aa20a830df2c8c756b9e569709a59073554) # Conflicts: # core/src/main/scala/chisel3/Module.scala # core/src/main/scala/chisel3/experimental/hierarchy/ModuleClone.scala * Resolve backport conflicts * Waive false positive binary compatibility errors Co-authored-by: Jack Koenig <koenig@sifive.com>
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