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path: root/src/test/scala/chiselTests/util/random/PRNGSpec.scala
AgeCommit message (Collapse)Author
2023-11-23cleanupAditya Naik
2022-01-10Apply scalafmtJack Koenig
Command: sbt scalafmtAll
2020-10-01Move Chisel3 to SPDX license conventions (#1604)Chick Markley
Change source and other relevant files to use SPDX license LICENSE file moved from src/ to ./ Changed license file to refer to this per recommendation using_spdx_license_list_short_identifiers WARNING: Tests fail with as of yet undiagnosed error ``` [error] Failed: Total 691, Failed 19, Errors 0, Passed 672, Ignored 15 [error] Failed tests: [error] chiselTests.QueueSpec [error] examples.VendingMachineGeneratorSpec [error] chiselTests.HarnessSpec [error] chiselTests.ConnectSpec [error] chiselTests.aop.SelectSpec [error] chiselTests.PopCountSpec [error] chiselTests.CloneModuleSpec [error] (Test / test) sbt.TestsFailedException: Tests unsuccessful [error] Total time: 379 s (06:19), completed Sep 30, 2020 12:38:17 AM sbt:chisel3> ```
2020-06-22Use ChiselStage in TestsSchuyler Eldridge
This migrates the tests to Chisel 3.4/FIRRTL 1.4. This primarily involves removing usages of deprecated methods including: - Remove usages of Driver - Use ChiselStage methods instead of BackendCompilationUtilities methods - Use Dependency API for custom transforms - Use extractCause to unpack StackError Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-09PRNG state UInt->Vec[Bool], make async reset safeSchuyler Eldridge
Changes the internal state of PRNG to use Vec[Bool] instead of UInt. This fixes an @aswaterman identified future problem with asynchronous reset. A register with an asynchronous reset can only be reset to a literal. Previously, an LFSR would store state as a UInt. If it was not parameterized with a seed it should have its least significant bit reset to something to avoid locking up. It's ideal to not reset the full UInt (better test coverage, decreased reset fanout). However, it's difficult to only reset one bit of a UInt. Conversely, it's trivial to reset one bit of a Vec[Bool]. This also moves PRNG/LFSR closer to a canonical representation of their internal state, i.e., it's natural to think of generalizing Vec[Bool] to arbitrary finite fields (Vec[A <: Field]) whereas UInt is tightly coupled to GF2. Minor updates: - Updates/fixes to some scaladoc - Add assertion to period test to make sure LFSR is changing Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-09Add Lfsr testsSchuyler Eldridge
Add LFSR tests using LFSR16 testing infrastructure. This also adds tests that are the same as the examples shown for LFSR scaladoc. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>