| Age | Commit message (Collapse) | Author |
|---|
|
|
|
Fixes #746
Also add test for https://github.com/freechipsproject/firrtl/issues/705
|
|
Fixes #482
|
|
* Require explicit connection to DontCare to generate "is invalid".
* Add tests for RefNotInitializedException.
Currently, we fail the when ... otherwise ...
* Disable ScalaTest shrinking on error in ComplexAssignSpec.
* fix broken merge; still some binding issues
* cleanup DontCare connection checks; add missing directions to test module IOs
* Have library code inherit compileOptions from the enclosing Module (if it exists).
* work around current firrtl uninitialized references with Strict compile options and explicitInvalidate
* more CompileOptions cleanup; move test-specific defines to package object
* minimize differences with master
* set default CompileOptions.explicitInvalidate to false until we fix the FIRRTL when issue
* ignore the StrictCompiler property checks (until CompileOptions.explicitInvalidate is defaulted to true)
* Revert "more CompileOptions cleanup; move test-specific defines to package object"
This reverts commit e4486edcba990d150e76e08a2fc6abca033556e0.
* Revert "work around current firrtl uninitialized references with Strict compile options and explicitInvalidate"
This reverts commit 426faa430a62c3dac2dbdf33044d3386d4243157.
* remove unused code
* Convert to binding-based DontCare implementation
* comment cleanup to minimize differences with master
* Tentatively remove possibly redundant DefInvalid on module ports.
* Respond to code review change request.
- backout build.sbt change
- correct indentation
- handle bulk of DontCare semantics in elemConnect()
- have DontCare extend Element, not Data (eliminate most Object specific methods
- add comments indicating reason for explicit DontCare connections
* Initialize test elements without requiring a DontCare.
* Respond to review change requests.
- DontCare should work on left or right side in BiDirectional connections
- call bind() to set DontCare binding instead of messing with internal variables
- DontCares are only equivalent with DontCares
- clean up processWhens() definition
* Eliminate DontCare connection to inputs in MonoConnect().
* Pull aggregates apart for the purpose of DontCare connections.
* Restore the explicit (conditionally executed) ports DefInvalidin ImplicitModule()
* Don't add DontCare's to the module list of _ids.
* Add missing DefInvalid() to LegacyModule().
* Respond to review requests: add DontCare BiConnect Vec, remove null parent hack to avoid addId(), initialize singletons early in Builder
* Move DontCare out of chisel3.experimental.
|
|
Addresses #419
cloneType is now marked (through comments only) as an internal API.
chiselCloneType deprecated (and changed to cloneTypeFull internally, analogous to cloneTypeWidth).
chiselTypeOf(data) introduced as the external API to get a chisel type from a hardware object
Intended usage: cloning is an implementation detail, and chisel types and hardware objects both should act as immutable types, with operations like Input(...), Reg(...), etc returning a copy and leaving the original unchanged. Hence, the clone operations are all deprecated.
Deletes what appears to be an unused Bundle companion object.
Input(...), Output(...), Flipped(...) require the object to be unbound
|
|
Rest of the binding refactor
|
|
* Partially revert 8e4ddc62db448b613ae327792e72defca4d115d4
It was an incomplete fix for handling Vec(0).
* Fix assignment from 0-entry Vec: add test
375e2b6a0a456c55298d82837d28986de6211ebc introduced a regression for bundles
containing zero-entry Vecs. Until zero-width UInts are supported, the
zero-entry Vecs need to be flattened out before doing asUInt/asTypeOf on
a bundle. Undoing that commit's replacement of Data.flatten with
Aggregate.getElements is the best interim fix.
|
|
Using the sample_element of the created wire is incorrect because Wires have no
direction so the Wire constructed for a Vec of Module IO was constructed
incorrectly. Fixes #569 and resolves #522.
|
|
This also allows asUInt/asTypeOf to work properly on those Bundles,
even though zero-width wire support is lacking.
|
|
Use fold(0) instead of reduce to handle the corner case.
|
|
* Revert "Change Vec creation to check if gen is lit (and hence needs to be declared)"
This reverts commit dc86e7e1734d6abacb739b488df1de231e6b41b2.
This may address #522 - using chiselCloneType (instead of cloneType) to preserve directionality.
* Add missing implicits to Vec.apply() signature.
* Use correct macro (CompileOptionsTransform) for indexWhere.
|
|
|
|
This is an odd one. Using log2Ceil directly results in a Verilator
compile error, presumably due to a FIRRTL zero-width wire bug.
|
|
Test for ucb-bar/firrtl#407
|
|
* Added vec IO tests for #104
* Added Vec test case for Reg of vecs
* Change Vec creation to check if gen is lit (and hence needs to be declared)
Fixes #104
* Fix tests (add IO())), Vec.fill()
* Fix deprecated usage.
* Add Binding IO() NPE fix so tests pass.
* Fix style - use space consistently.
* Fix style - use space consistently.
|
|
|
|
|
|
|
|
|
|
|
|
Massage CompileOption names in an attempt to preserve default (Strict) CompileOptions in the absence of explicit imports.
NOTE: Since the default is now strict, we may encounter errors when we generate connections for clients (i.e., in Vec.do_apply() when we wire up a sequence).
We should really thread the CompileOptions through the macro system so the client's implicits are used.
|
|
Eliminate builder compileOptions.
|
|
Remove .Lit(x) usage.
Undo "private" scope change.
Change "firing" back to "fire".
Add package level NODIR definition.
|
|
|
|
|
|
|
|
|
|
|
|
because the sole remaining use of toBits in chiselTests was to compare to Vectors declared differently but with same underlying bits.
Making at toBits was problematic because it did not support === method.
Changed Vec and Bundle to both support toUInt()
Note: If toBits is actually needed now, one can use toInt().toBits()
|
|
* chiselTests: include an example of two empty Vectors killing FIRRTL
* Aggregate: fix a bug whereby Vec[T] was using equals/hashCode of Seq
In Chisel, two vectors are NOT equal just if their contents are equal.
For example, two empty vectors should not be considered equal. This
patch makes Vec use the HasId._id for equality like other Chisel types.
Without this fix, Bundle.namedElts.seen: HashSet[Data]() will eliminate
one of the named vectors and emit bad IR.
|
|
|
|
|
|
Gate assert, printf, stop by reset
Fix testbenches that never worked
Change simulation prints to display cycle at which test was signaled to end, not when simulator stops
Better documentation for Counter
|
|
|
|
In addition to removing all the extraneous Driver invocations that created various top-level Parameters instances,
this commit also lays the groundwork for stanza-firrtl/verilator based testing of Modules that extend BasicTester.
The execution-based tests have been updated accordingly. They will only succeed if firrtl and verilator binaries have been installed.
Further work is needed on individual tests to use assertions instead of .io.error.
|
|
|
|
|
|
|
|
|
