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Command:
sbt scalafmtAll
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Change source and other relevant files to use SPDX license
LICENSE file moved from src/ to ./
Changed license file to refer to this per recommendation
using_spdx_license_list_short_identifiers
WARNING: Tests fail with as of yet undiagnosed error
```
[error] Failed: Total 691, Failed 19, Errors 0, Passed 672, Ignored 15
[error] Failed tests:
[error] chiselTests.QueueSpec
[error] examples.VendingMachineGeneratorSpec
[error] chiselTests.HarnessSpec
[error] chiselTests.ConnectSpec
[error] chiselTests.aop.SelectSpec
[error] chiselTests.PopCountSpec
[error] chiselTests.CloneModuleSpec
[error] (Test / test) sbt.TestsFailedException: Tests unsuccessful
[error] Total time: 379 s (06:19), completed Sep 30, 2020 12:38:17 AM
sbt:chisel3>
```
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ChiselStage$ helpers (#1566)
* Add ChiselPhase
* Use ChiselPhase in ChiselStage, remove targets
Switch from a one-off PhaseManager inside ChiselStage to actually
using the newly added ChiselPhase. This removes the targets
method (and API) from ChiselStage.
* Stop writing to files in ChiselStage$ methods
Change the ChiselStage companion object methods, elaborate and
convert, to not write files. Under the hood, these are switched from
using ChiselStage (which, like all phases, will write files) to using
ChiselPhase.
* Test that ChiselStage$ methods write no files
Modify existing ChiselStage object method tests to check that no files
are written.
* Expand ChiselStage$ API with more helpers
This adds additional methods to the ChiselStage object for going
directly from a Chisel module to a string including: CHIRRTL, high
FIRRTL IR, Verilog, and SystemVerilog.
Differing from their ChiselStage class counterparts, these take no
arguments other than the module and write no files.
* Add tests of new ChiselStage$ helper methods
* Use ChiselStage object in tests
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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* Fix emit{Firrtl,Verilog} for CustomFileEmission
Change ChiselStage helper methods for emitting FIRRTL (emitFirrtl) and
Verilog (emitVerilog) to look for Circuit and Verilog annotations
instead of DeletedAnnotations. This is needed after migrating to the
CustomFileEmission mixin in FIRRTL where FIRRTL will no longer delete
emitter annotations.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
* Use CustomFileEmission for ChiselCircuitAnnotation
Removes the explicit chisel3.phases.Emitter and instead does emission
with a CustomFileEmission mixin to ChiselCircuitAnnotation. This then
prevents the need for passing around DeletedAnnotations. As a
consequence, I removed an unnecessary run of a second Converter in the
Driver.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
* Fix tests for use of CustomFileEmission trait
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
* Fixes for newer CustomFileEmission API
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This migrates the tests to Chisel 3.4/FIRRTL 1.4. This primarily
involves removing usages of deprecated methods including:
- Remove usages of Driver
- Use ChiselStage methods instead of BackendCompilationUtilities
methods
- Use Dependency API for custom transforms
- Use extractCause to unpack StackError
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
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* Update style warnings now that subprojects are aggregated.
Use "scalastyle-test-config.xml" for scalastyle config in tests.
Enable "_" in method names and accept method names ending in "_=".
Re-sync scalastyle-test-config.xml with scalastyle-config.xml
* Remove bogus tests that crept in with git add
* Add missing import.
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