chiselX - Chisel with SFC compatibility

Age	Commit message (Collapse)	Author
2017-02-07	Add generateFirrtl() method to ChiselSpec.scala (#423)	Jim Lawson

2017-01-31	Add compile [to Verilog] to ChiselRunners	Jack

2016-11-14	Add checks for misuse or omission of Module()	Jack
	Implemented by adding a Boolean to check for alternating invocations of object Module.apply and the constructor of abstract class Module. Fixes #192
2016-06-20	Rename "package", "import", and explicit references to "chisel3".	Jim Lawson

2016-06-08	Rename Chisel -> chisel in tests	ducky

2016-05-04	Multiple assign tester	ducky
	Closes #90
2016-01-30	Add BlackBox support and test, refactor execute => assertTesterPasses	ducky

2015-12-06	Split internal and FIRRTL packages	ducky

2015-11-04	Supply smaller values for generatorDrivenConfig to reduce test time.	Henry Cook

2015-11-04	Remove Parameters library and refactor Driver.	Henry Cook
	In addition to removing all the extraneous Driver invocations that created various top-level Parameters instances, this commit also lays the groundwork for stanza-firrtl/verilator based testing of Modules that extend BasicTester. The execution-based tests have been updated accordingly. They will only succeed if firrtl and verilator binaries have been installed. Further work is needed on individual tests to use assertions instead of .io.error.
2015-10-23	Fix stylistic issues and document standard Chisel generators	ducky

2015-10-23	Add Scalaland unit tests for Reg	ducky

2015-10-23	Whitespace scalastyle fixes for tests	ducky

2015-08-14	more tests	Henry Cook

2015-08-14	Add Vec tests. Do a better job of generating widths.	Henry Cook

2015-08-14	added MulLookup and Tbl tests	Henry Cook

2015-08-13	add decoder test	Henry Cook

2015-08-13	Counter tests	Henry Cook

2015-08-13	complexassign test	Henry Cook

2015-08-13	testing improvements	Henry Cook

2015-08-13	minor tweaks	Henry Cook

2015-08-13	Use chiselTests package; add copyright notice.	Jim Lawson

2015-08-13	rename package (lowercase)	Jim Lawson