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(cherry picked from commit f9aee1f72744abc6ee13aafc4d1a51a2783cbab8)
Co-authored-by: Jack Koenig <koenig@sifive.com>
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Command:
sbt scalafmtAll
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Chisel projects no longer need -Xsource:2.11 when compiling with Scala
2.12.
Autowrapping of "val io" for compatibility mode Modules is now
implemented using reflection instead of calling the virtual method.
Also move Chisel.BlackBox to new chisel3.internal.LegacyBlackBox
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Change source and other relevant files to use SPDX license
LICENSE file moved from src/ to ./
Changed license file to refer to this per recommendation
using_spdx_license_list_short_identifiers
WARNING: Tests fail with as of yet undiagnosed error
```
[error] Failed: Total 691, Failed 19, Errors 0, Passed 672, Ignored 15
[error] Failed tests:
[error] chiselTests.QueueSpec
[error] examples.VendingMachineGeneratorSpec
[error] chiselTests.HarnessSpec
[error] chiselTests.ConnectSpec
[error] chiselTests.aop.SelectSpec
[error] chiselTests.PopCountSpec
[error] chiselTests.CloneModuleSpec
[error] (Test / test) sbt.TestsFailedException: Tests unsuccessful
[error] Total time: 379 s (06:19), completed Sep 30, 2020 12:38:17 AM
sbt:chisel3>
```
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This mechanism is not enabled and should not change the behavior of existing tests
A following PR will deliver a switch that will allow changing the backend.
The reasons for this PR
- Treadle tests run much faster, enabling quicker debugging and CI cycles
- This will help ensure fidelity of Treadle to the Verilator backend
A few tests are marked as verilator only due to black box limitations
Change treadle to a direct dependency
I tried to make it a test only dependency but the TesterDriver sits in src/main requiring that
regular compile have access to treadle
Oops, made treadle the default
A number of changes in response to @ducky64 review
- made backend check clearer and add error handling for multiple backends specified
- Fixed duplicate TargetDirAnnotation uses in Treadle backend
- Cleaned up BlackBox test formatting
- Undid unnecessary debugging changes from Counter
- Undid .gitignore change, that should be on another PR
A number of changes in response to @ducky64 review
- Undid debugging changes made to BitWiseOps
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This migrates the tests to Chisel 3.4/FIRRTL 1.4. This primarily
involves removing usages of deprecated methods including:
- Remove usages of Driver
- Use ChiselStage methods instead of BackendCompilationUtilities
methods
- Use Dependency API for custom transforms
- Use extractCause to unpack StackError
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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* Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3
and deal with the subsequent fallout.
* Move Aggregate, Clock, Mem, Printf, Reg
* Move almost all chisel3.core definitions to chisel3 or chisel3.experimental
* Revive core package object to provide aliases for moved definitions.
* Cleanup package definitions; eliminate ambiguous implicits
* Move more definitions to experimental.
Extract BaseModule, DataMirror, ExtModule, IO into their own files.
* Put BitPat back in chisel3.util
* More experimental motion - avoid multiple import definitions.
* Add experimental.FixedPoint alias
* Add EnumType definition to core package.
Update deprecated messages to refer to correct object
* Move FixedPoint into the experimental package (but keep it in Bits.scala).
* Add missing implicits to core/package - compatibility
* Cleanup: update ScalaDoc references; remove unused imports
* Add Reset alias to core/package
* Use common 3.2 version in deprecation warning
* Move Binding from core to internal.
* Optimize imports.
* Repair IntelliJ's overly cleanliness.
* Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3
and deal with the subsequent fallout.
Move Aggregate, Clock, Mem, Printf, Reg
Move almost all chisel3.core definitions to chisel3 or chisel3.experimental
Revive core package object to provide aliases for moved definitions.
Cleanup package definitions; eliminate ambiguous implicits
Move more definitions to experimental.
Extract BaseModule, DataMirror, ExtModule, IO into their own files.
Add EnumType definition to core package.
Update deprecated messages to refer to correct object
Move FixedPoint into the experimental package (but keep it in Bits.scala).
Add missing implicits to core/package - compatibility
Cleanup: update ScalaDoc references; remove unused imports
Use common 3.2 version in deprecation warning
Move Binding from core to internal.
* Change == to reference equality (eq) in Data print (#1044)
* Remove @chiselName from MixedVec (#1045)
* Fix enum annotations (#936)
* Turned off strong enum annotations because they weren't working with Vec
indexes
* Add new EnumVecAnnotation for vecs of enums and vecs of bundles with
enum fields
* Changed Clock's width parameter back to a fixed constant value of 1
* Fixed enum annotations for Vecs of Bundles which contain enum elements
* Fixed usage of "when/otherwise" to use consistent style
* Add Record to type hierarchy documentation
* Undeprecate isLit (#1048)
* move doNotDedup to experimental (#1008)
* Aggregate coverage - aggregate tests but not publishing (#1040)
Discover a working combination of aggregate usage to enable coverage of subproject testing but publish a single Jar.
Use "scalastyle-test-config.xml" for scalastyle config in tests.
Enable "_" in method names and accept method names ending in "_=".
Re-sync scalastyle-test-config.xml with scalastyle-config.xml
This should finally fix #772.
* Check field referential equality in autoclonetype (#1047)
* Allow naming annotation to work outside builder context (#1051)
* Try to eliminate JVM hang due to static initialization deadlock (#1053)
* Make core.DontCare private to chisel3 (#1054)
Force clients to access 'DontCare' through the chisel3 package to ensure it's created as a chisel3 object and not a client object.
* Ignore empty aggregates elements when binding aggregate direction (#946)
Previously, including an empty aggregate in a Bundle would cause
a MixedDirectionAggregateException because it has no elements and thus
doesn't have a direction
* Add SampleElementBinding for Vec sample elements
* Add ActualDirection.Empty for bound empty aggregates
* Detect bundle aliasing (#1050)
* Implement connectFromBits in ChiselEnum (#1052)
This is necessary to use ChiselEnum in aggregates where things are
casted using .asTypeOf
* Optimize imports.
* Move Analog to experimental.
* More repackage cleanup - reduce differences with master.
* Cleanup chisel3 references.
* More chisel3 reference cleanup.
* Merge cleanup.
* Remove unused import
* Bump core deprecation to 3.3
* Move DontCare back into Data.scala inside package internal
* Re-indent experimental/internal package code
* Move code back to original files - facilitate comparison with other branches
* Some code motion, update imports, minimize master differences
Move exceptions up to chisel3 package object - they're part of the interface.
* More master diff minimization.
* Try to eliminate JVM hang due to static initialization deadlock (#1053)
* Ignore empty aggregates elements when binding aggregate direction (#946)
Previously, including an empty aggregate in a Bundle would cause
a MixedDirectionAggregateException because it has no elements and thus
doesn't have a direction
* Add SampleElementBinding for Vec sample elements
* Add ActualDirection.Empty for bound empty aggregates
* Implement connectFromBits in ChiselEnum (#1052)
This is necessary to use ChiselEnum in aggregates where things are
casted using .asTypeOf
* Move Analog to experimental.
More repackage cleanup - reduce differences with master.
Cleanup chisel3 references.
More chisel3 reference cleanup.
* Fix wrong directionality for Vec(Flipped())
Create Chisel IR Port() in a way that Converter is happy with.
Also add more extensive test suite for future-proofing.
Close #1063
* Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3
and deal with the subsequent fallout.
Move Aggregate, Clock, Mem, Printf, Reg
Move almost all chisel3.core definitions to chisel3 or chisel3.experimental
Revive core package object to provide aliases for moved definitions.
Cleanup package definitions; eliminate ambiguous implicits
Move more definitions to experimental.
Extract BaseModule, DataMirror, ExtModule, IO into their own files.
Put BitPat back in chisel3.util
More experimental motion - avoid multiple import definitions.
Add experimental.FixedPoint alias
Add EnumType definition to core package.
Update deprecated messages to refer to correct object
Move FixedPoint into the experimental package (but keep it in Bits.scala).
Add missing implicits to core/package - compatibility
Cleanup: update ScalaDoc references; remove unused imports
Add Reset alias to core/package
Use common 3.2 version in deprecation warning
Move Binding from core to internal.
Optimize imports.
Repair IntelliJ's overly cleanliness.
Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3
and deal with the subsequent fallout.
Move Aggregate, Clock, Mem, Printf, Reg
Move almost all chisel3.core definitions to chisel3 or chisel3.experimental
Revive core package object to provide aliases for moved definitions.
Cleanup package definitions; eliminate ambiguous implicits
Move more definitions to experimental.
Extract BaseModule, DataMirror, ExtModule, IO into their own files.
Add EnumType definition to core package.
Update deprecated messages to refer to correct object
Move FixedPoint into the experimental package (but keep it in Bits.scala).
Add missing implicits to core/package - compatibility
Cleanup: update ScalaDoc references; remove unused imports
Use common 3.2 version in deprecation warning
Move Binding from core to internal.
Optimize imports.
Merge cleanup.
Remove unused import
Bump core deprecation to 3.3
Move DontCare back into Data.scala inside package internal
Re-indent experimental/internal package code
Move code back to original files - facilitate comparison with other branches
Some code motion, update imports, minimize master differences
Move exceptions up to chisel3 package object - they're part of the interface.
More master diff minimization.
Fix minor discrepancies with repackagecore-testbed
* Remove redundant imports
As part of its import updating process, IntelliJ converted some import statements to `import package.{object, _}`. Is this intended to show an explicit dependency on `package.object` and a further dependency on `package` implicits? Unsure. Replace these with `import package._`
* Move the BaseModule object into the internal package.
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Part 1 of mega-change in #578
Major notes:
- Input(...) and Output(...) now (effectively) recursively override their elements' directions
- Nodes given userDirection (Input, Output, Flip - what the user assigned to _that_ node) and actualDirection (Input, Output, None, but also Bidirectional and BidirectionalFlip for mostly Aggregates), because of the above (since a higher-level Input(...) can override the locally specified user direction).
- DataMirror (node reflection APIs) added to chisel3.experimental. This provides ways to query the user given direction of a node as well as the actual direction.
- checkSynthesizable replaced with requireIsHardware and requireIsChiselType and made available in chisel3.experimental.
Internal changes notes:
- toType moved into Emitter, this makes the implementation cleaner especially considering that Vec types can't be flipped in FIRRTL. This also more clearly separates Chisel frontend from FIRRTL emission.
- Direction separated from Bindings, both are now fields in Data, and all nodes are given hierarchical directions (Aggregates may be Bidirectional). The actualDirection at the Element (leaf) level should be the same as binding directions previously.
- Bindings are hierarchical, children (of a, for example, Bundle) have a ChildBinding that points to their parent. This is different than the previous scheme where Bindings only applied at the Element (leaf) level.
- Lots of small misc clean up.
Future PRs will address other parts of #578, including stricter direction checks that aren't a side-effect of this internal refactor, stricter checks and splitting of binding operations (Wire vs. WireInit), and node operations not introduced here (getType and deprecation of chiselCloneType). Since those shouldn't mess with internals, those should be much smaller.
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* Mark Annotation and FixedPoint as experimental
Fix tests and other references to these constructs
* Made experimental imports more specific where possible
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Also restrict black boxes to not allow hardware inside of them since it was
being silently dropped anyway.
Resolves #289
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Massage CompileOption names in an attempt to preserve default (Strict) CompileOptions in the absence of explicit imports.
NOTE: Since the default is now strict, we may encounter errors when we generate connections for clients (i.e., in Vec.do_apply() when we wire up a sequence).
We should really thread the CompileOptions through the macro system so the client's implicits are used.
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Eliminate builder compileOptions.
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Remove .Lit(x) usage.
Undo "private" scope change.
Change "firing" back to "fire".
Add package level NODIR definition.
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The old blackbox behavior still emitted extmodules that have a
clk, reset pin and prepended all io's with io_ (ultimately). Most
verilog modules do not follow this distinction (or use a slightly
different name for clock and so on).
Thus, instead BlackBox has been rewritten to not assume a clk or
reset pin. Instead, the io Bundle specified is flattened directly
into the Module.ports declaration. The tests have been rewritten
to compensate for this. Also, added a test that uses the clock pin.
As a secondary change, the _clock and _reset module parameters were
bad for two reasons. One, they used null as a default, which is a
scala best practices violation. Two, they were just not good names.
Instead the primary constructor has been rewritten to take an
Option[Clock] called override_clock and an Option[Bool] called
override_reset, which default to None. (Note how the getOrElse call
down below is much more natural now.)
However, users may not want to specify the Some(their_clock) so I
also added secondary constructors that take parameters named clock
and reset and wrap them into Some calls into the primary constructor.
This is a better UX because now you can just stipulate clock=blah in
instantiation of that module in symmetry with using the clock in the
definition of the module by invoking clock.
PS: We could also back out of allowing any overrides via the Module
constructor and just require the instantiating Module to do
submodule.clock := newclock, etc.
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