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Command:
sbt scalafmtAll
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Change source and other relevant files to use SPDX license
LICENSE file moved from src/ to ./
Changed license file to refer to this per recommendation
using_spdx_license_list_short_identifiers
WARNING: Tests fail with as of yet undiagnosed error
```
[error] Failed: Total 691, Failed 19, Errors 0, Passed 672, Ignored 15
[error] Failed tests:
[error] chiselTests.QueueSpec
[error] examples.VendingMachineGeneratorSpec
[error] chiselTests.HarnessSpec
[error] chiselTests.ConnectSpec
[error] chiselTests.aop.SelectSpec
[error] chiselTests.PopCountSpec
[error] chiselTests.CloneModuleSpec
[error] (Test / test) sbt.TestsFailedException: Tests unsuccessful
[error] Total time: 379 s (06:19), completed Sep 30, 2020 12:38:17 AM
sbt:chisel3>
```
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This mechanism is not enabled and should not change the behavior of existing tests
A following PR will deliver a switch that will allow changing the backend.
The reasons for this PR
- Treadle tests run much faster, enabling quicker debugging and CI cycles
- This will help ensure fidelity of Treadle to the Verilator backend
A few tests are marked as verilator only due to black box limitations
Change treadle to a direct dependency
I tried to make it a test only dependency but the TesterDriver sits in src/main requiring that
regular compile have access to treadle
Oops, made treadle the default
A number of changes in response to @ducky64 review
- made backend check clearer and add error handling for multiple backends specified
- Fixed duplicate TargetDirAnnotation uses in Treadle backend
- Cleaned up BlackBox test formatting
- Undid unnecessary debugging changes from Counter
- Undid .gitignore change, that should be on another PR
A number of changes in response to @ducky64 review
- Undid debugging changes made to BitWiseOps
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This migrates the tests to Chisel 3.4/FIRRTL 1.4. This primarily
involves removing usages of deprecated methods including:
- Remove usages of Driver
- Use ChiselStage methods instead of BackendCompilationUtilities
methods
- Use Dependency API for custom transforms
- Use extractCause to unpack StackError
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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* Move dontTouch out of experimental package.
* Move RawModule, MultiIOModule out of experimental.
* Respond to comments - Move LagacyModule from experimental to internal.
*NOTE*: At some point, these module definitions (especially those in separate packages) should be moved to individual files at the appropriate location in the source tree. The current organization is purely to support comparison with prior versions.
* Fix up a few more imports.
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Short-term patch to enable this useful behavior. In the future, we may want to rearchitect the type system and/or rethink the more edge-case connect behavior.
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* IO(Analog) fixed for RawModule
* Add a Analog Port for RawModule test & spec
* Fixes around Module instantiation and ports in AnalogPortRawModuleTest
* Shorten Comment
* Add Data.isSynthesizable to distinguish SampleElementBinding
This helps clarify the notion of being bound but not hardware.
Data.topBindingOpt is now used to get the *actual* top binding,
including across SampleElements (eg. in Analog checking that the top is
bound to a Port or a Wire)
* Fix pretty printing for Vec
* Refactor tests for Vec of Analog, add test for Vec of Bundle of Analog
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Rest of the binding refactor
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Used for stitching Verilog inout through Chisel Modules (from BlackBox
to BlackBox)
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