summaryrefslogtreecommitdiff
path: root/src/test/scala/chiselTests/AnalogIntegrationSpec.scala
AgeCommit message (Collapse)Author
2017-02-08Add Analog typeJack Koenig
Used for stitching Verilog inout through Chisel Modules (from BlackBox to BlackBox)
generated by cgit v1.2.3 (git 2.25.1) at 2026-03-01 20:49:00 +0000