| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2019-01-09 | Avoid procedural wire assignment in test resource | Schuyler Eldridge | |
| Verilator 4.008 dropped the hammer on procedural wire assignment to align with the IEEE standard (first I've heard of this, though). The VerilogVendingMachine.v test resource will error in Verilator 4.008 with a PROCASSWIRE error if you try to compile it. This fixes that example to only assign to a register. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> | |||
| 2017-07-28 | Black box top-level IO fix (#655) | Richard Lin | |
| 2017-05-11 | Scope resources - move them down into chisel3 directory - fixes #549 (#610) | Jim Lawson | |
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index : chiselX | |
| Chisel with SFC compatibility |
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