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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-Authored-By: chick <chick@qrhino.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-Authored-By: chick <chick@qrhino.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This adds the following FIRRTL Annotations to Chisel:
- NoRunFirrtlCompilerAnnotation
- PrintFullStackTraceAnnotation
- ChiselGeneratorAnnotation
- ChiselCircuitAnnotation
- ChiselOutputFileAnnotation
This includes tests for ChiselGeneratorAnnotation as this Annotation
is able to be constructed from a String and to elaborate itself.
Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-Authored-By: chick <chick@qrhino.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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* Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3
and deal with the subsequent fallout.
* Move Aggregate, Clock, Mem, Printf, Reg
* Move almost all chisel3.core definitions to chisel3 or chisel3.experimental
* Revive core package object to provide aliases for moved definitions.
* Cleanup package definitions; eliminate ambiguous implicits
* Move more definitions to experimental.
Extract BaseModule, DataMirror, ExtModule, IO into their own files.
* Put BitPat back in chisel3.util
* More experimental motion - avoid multiple import definitions.
* Add experimental.FixedPoint alias
* Add EnumType definition to core package.
Update deprecated messages to refer to correct object
* Move FixedPoint into the experimental package (but keep it in Bits.scala).
* Add missing implicits to core/package - compatibility
* Cleanup: update ScalaDoc references; remove unused imports
* Add Reset alias to core/package
* Use common 3.2 version in deprecation warning
* Move Binding from core to internal.
* Optimize imports.
* Repair IntelliJ's overly cleanliness.
* Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3
and deal with the subsequent fallout.
Move Aggregate, Clock, Mem, Printf, Reg
Move almost all chisel3.core definitions to chisel3 or chisel3.experimental
Revive core package object to provide aliases for moved definitions.
Cleanup package definitions; eliminate ambiguous implicits
Move more definitions to experimental.
Extract BaseModule, DataMirror, ExtModule, IO into their own files.
Add EnumType definition to core package.
Update deprecated messages to refer to correct object
Move FixedPoint into the experimental package (but keep it in Bits.scala).
Add missing implicits to core/package - compatibility
Cleanup: update ScalaDoc references; remove unused imports
Use common 3.2 version in deprecation warning
Move Binding from core to internal.
* Change == to reference equality (eq) in Data print (#1044)
* Remove @chiselName from MixedVec (#1045)
* Fix enum annotations (#936)
* Turned off strong enum annotations because they weren't working with Vec
indexes
* Add new EnumVecAnnotation for vecs of enums and vecs of bundles with
enum fields
* Changed Clock's width parameter back to a fixed constant value of 1
* Fixed enum annotations for Vecs of Bundles which contain enum elements
* Fixed usage of "when/otherwise" to use consistent style
* Add Record to type hierarchy documentation
* Undeprecate isLit (#1048)
* move doNotDedup to experimental (#1008)
* Aggregate coverage - aggregate tests but not publishing (#1040)
Discover a working combination of aggregate usage to enable coverage of subproject testing but publish a single Jar.
Use "scalastyle-test-config.xml" for scalastyle config in tests.
Enable "_" in method names and accept method names ending in "_=".
Re-sync scalastyle-test-config.xml with scalastyle-config.xml
This should finally fix #772.
* Check field referential equality in autoclonetype (#1047)
* Allow naming annotation to work outside builder context (#1051)
* Try to eliminate JVM hang due to static initialization deadlock (#1053)
* Make core.DontCare private to chisel3 (#1054)
Force clients to access 'DontCare' through the chisel3 package to ensure it's created as a chisel3 object and not a client object.
* Ignore empty aggregates elements when binding aggregate direction (#946)
Previously, including an empty aggregate in a Bundle would cause
a MixedDirectionAggregateException because it has no elements and thus
doesn't have a direction
* Add SampleElementBinding for Vec sample elements
* Add ActualDirection.Empty for bound empty aggregates
* Detect bundle aliasing (#1050)
* Implement connectFromBits in ChiselEnum (#1052)
This is necessary to use ChiselEnum in aggregates where things are
casted using .asTypeOf
* Optimize imports.
* Move Analog to experimental.
* More repackage cleanup - reduce differences with master.
* Cleanup chisel3 references.
* More chisel3 reference cleanup.
* Merge cleanup.
* Remove unused import
* Bump core deprecation to 3.3
* Move DontCare back into Data.scala inside package internal
* Re-indent experimental/internal package code
* Move code back to original files - facilitate comparison with other branches
* Some code motion, update imports, minimize master differences
Move exceptions up to chisel3 package object - they're part of the interface.
* More master diff minimization.
* Try to eliminate JVM hang due to static initialization deadlock (#1053)
* Ignore empty aggregates elements when binding aggregate direction (#946)
Previously, including an empty aggregate in a Bundle would cause
a MixedDirectionAggregateException because it has no elements and thus
doesn't have a direction
* Add SampleElementBinding for Vec sample elements
* Add ActualDirection.Empty for bound empty aggregates
* Implement connectFromBits in ChiselEnum (#1052)
This is necessary to use ChiselEnum in aggregates where things are
casted using .asTypeOf
* Move Analog to experimental.
More repackage cleanup - reduce differences with master.
Cleanup chisel3 references.
More chisel3 reference cleanup.
* Fix wrong directionality for Vec(Flipped())
Create Chisel IR Port() in a way that Converter is happy with.
Also add more extensive test suite for future-proofing.
Close #1063
* Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3
and deal with the subsequent fallout.
Move Aggregate, Clock, Mem, Printf, Reg
Move almost all chisel3.core definitions to chisel3 or chisel3.experimental
Revive core package object to provide aliases for moved definitions.
Cleanup package definitions; eliminate ambiguous implicits
Move more definitions to experimental.
Extract BaseModule, DataMirror, ExtModule, IO into their own files.
Put BitPat back in chisel3.util
More experimental motion - avoid multiple import definitions.
Add experimental.FixedPoint alias
Add EnumType definition to core package.
Update deprecated messages to refer to correct object
Move FixedPoint into the experimental package (but keep it in Bits.scala).
Add missing implicits to core/package - compatibility
Cleanup: update ScalaDoc references; remove unused imports
Add Reset alias to core/package
Use common 3.2 version in deprecation warning
Move Binding from core to internal.
Optimize imports.
Repair IntelliJ's overly cleanliness.
Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3
and deal with the subsequent fallout.
Move Aggregate, Clock, Mem, Printf, Reg
Move almost all chisel3.core definitions to chisel3 or chisel3.experimental
Revive core package object to provide aliases for moved definitions.
Cleanup package definitions; eliminate ambiguous implicits
Move more definitions to experimental.
Extract BaseModule, DataMirror, ExtModule, IO into their own files.
Add EnumType definition to core package.
Update deprecated messages to refer to correct object
Move FixedPoint into the experimental package (but keep it in Bits.scala).
Add missing implicits to core/package - compatibility
Cleanup: update ScalaDoc references; remove unused imports
Use common 3.2 version in deprecation warning
Move Binding from core to internal.
Optimize imports.
Merge cleanup.
Remove unused import
Bump core deprecation to 3.3
Move DontCare back into Data.scala inside package internal
Re-indent experimental/internal package code
Move code back to original files - facilitate comparison with other branches
Some code motion, update imports, minimize master differences
Move exceptions up to chisel3 package object - they're part of the interface.
More master diff minimization.
Fix minor discrepancies with repackagecore-testbed
* Remove redundant imports
As part of its import updating process, IntelliJ converted some import statements to `import package.{object, _}`. Is this intended to show an explicit dependency on `package.object` and a further dependency on `package` implicits? Unsure. Replace these with `import package._`
* Move the BaseModule object into the internal package.
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This moves the documentation for loadMemoryFromFile onto the object as
opposed to the apply method. This includes additional cleanup in terms
of fixing uses of "$", topical grammar/capitalization, and adding more
outbound links.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Changes the internal state of PRNG to use Vec[Bool] instead of UInt.
This fixes an @aswaterman identified future problem with asynchronous
reset.
A register with an asynchronous reset can only be reset to a literal.
Previously, an LFSR would store state as a UInt. If it was not
parameterized with a seed it should have its least significant bit
reset to something to avoid locking up. It's ideal to not reset the
full UInt (better test coverage, decreased reset fanout). However,
it's difficult to only reset one bit of a UInt. Conversely, it's
trivial to reset one bit of a Vec[Bool]. This also moves PRNG/LFSR
closer to a canonical representation of their internal state, i.e.,
it's natural to think of generalizing Vec[Bool] to arbitrary finite
fields (Vec[A <: Field]) whereas UInt is tightly coupled to GF2.
Minor updates:
- Updates/fixes to some scaladoc
- Add assertion to period test to make sure LFSR is changing
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Builds out PRNG and LFSR type hierarchy. PRNG is the base class of
LFSR of which Galois and Fibonacci are concrete implementations.
PRNGs contain state (a UInt) and an update (delta) function. They have
a compile-time optional seed to set the PRNG state. The seed/state can
also be set at run-time. PRNGs can be run-time parameterized based on
how many updates they should do per cycle and whether or not to send
the seed through step-count state updates before loading it. (h/t
@jwright6323)
LFSRs are parameterized in a reduction operation (XOR or XNOR). An
LFSR that does NOT have a seed will be automatically initialized to a
minimally safe state (set/reset one bit) based on their reduction
operation. (h/t @aswaterman)
Adds Galois and Fibonacci LFSRs that define appropriate update
functions. Companion objects provide helpers to automatically generate
maximal period variants. Taps are provide for a very large set of
widths. The LFSR companion object provides an apply method to generate
a Fibonacci LFSR random variable (like the old LFSR16).
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- Introduce internal helper `castToInt`, which issues an error when the input
BigInt can't be represented as Int.
- Use `castToInt` wherever we were using `toInt` in a potentially unsafe way.
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* Update style warnings now that subprojects are aggregated.
Use "scalastyle-test-config.xml" for scalastyle config in tests.
Enable "_" in method names and accept method names ending in "_=".
Re-sync scalastyle-test-config.xml with scalastyle-config.xml
* Remove bogus tests that crept in with git add
* Add missing import.
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This changes from using the chiselname annotation on Pipe.apply to
using an explicit TransitName. This results in an improved name for
created valid and bits registers.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Co-Authored-By: ducky64 <elpato25@gmail.com>
Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@gmail.com>
Co-Authored-By: Edward Wang <edward.c.wang@compdigitec.com>
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* Add HasBlackBoxPath trait
* Use 'setResource' instead of 'addResource'
* Add ScalaDoc
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Co-Authored-By: schoeberl <martin@jopdesign.com>
Co-Authored-By: Edward Wang <edward.c.wang@compdigitec.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Close #1009
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* Update documentation for LSFR16
- Moved bulk of comments to object.
- Added an example
- Added functional test
- example based on section of test
* Update documentation for LSFR16
- Moved bulk of comments to object.
- Added an example
- Added functional test
- example based on section of test
* Update documentation for LSFR16
- Fixed typos in LFSR
- Reduce trials a little
- Add test of LFSR period
* Update documentation for LSFR16
- Fixed remaining LSFR, arrgh
- Removed intellij specific warning suppressor
- Fixed comments/scaladoc wording and case.
* Update documentation for LSFR16
- Use printable interpolator as example of printing out a Vec
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This compresses the Scaladoc for BoringUtils slightly by using 120
character lines and removing unnecessary whitespace.
This also changes the poorly named "dedup" parameter to the what it
actually is: "disableDedup".
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This fixes a bug where BoringUtils non-hierarchical sinks would be
deduplicated even when specified that they should not be.
h/t @ucbjrl for discovering this!
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Module class names (#994)
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JDK 11 `java.lang.String#lines` conflicts with Scala `StringOps#lines`.
This has been fixed in scalac 2.12.8 but projects using 2.11 in their
cross-build need the `Predef.augmentString` patch.
[Scala bug & fix reference](https://github.com/scala/bug/issues/11125)
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- Trim stack trace to show better, reduced information to the user
- Add --full-stacktrace to FIRRTL option to show full stack trace
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Resolves #917
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Quickfix for LoadMemoryTransform that gets this to work with Instance
Annotations. The new Instance Annotations caused a corner case where a
LoadMemoryAnnotation would be duplicated (via update/renaming) and the
resulting annotation would differ from the original in only their
originalMemoryNameOpt field. This corrects that by having the
ChiselLoadMemoryAnnotation also emit the originalMemoryNameOpt field where
it did not previously.
First part of a fix for freechipsproject/firrtl#922.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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* Added new strongly-typed enum construct called "StrongEnum". "StrongEnum" will automatically generate annotations that HDL backends can use to mark components as enums
Removed "override val width" constructor parameter from "Element" so that classes with variable widths, like the new strong enums, can inherit from it
Changed the parameter types of certain functions, such as "switch", "is", and "LitArg.bindLitArg" from "Bits" to "Element", so that they can take the new strong enums as arguments
* Added tests for the new strong enums
* Changed StrongEnum exception names and made sure in StrongEnum tests that the correct types of exceptions are thrown
* Fixed bug where an enum's global annotation would not be set if it was used in multiple circuits
Made styling changes to StrongEnum.scala
* Reverted accidental changes to the AnnotatingDiamond test
* Changed the API for casting non-literal UInts to enums
Added an isValid function that checks whether or not enums have valid values
Calling getWidth on an enum's companion object now returns a BigInt instead of an Int
* Casting a literal to an enum using the StrongEnum.castFromNonLit(n) function is now simply a wrapper for StrongEnum.apply(n)
* Fixed compilation bug
* * Added "next" method to EnumType
* Renamed "castFromNonLit" to "fromBits"
* The FSM example in the test/scala/cookbook now uses StrongEnums
* * Changed strong enum API, so that users no longer have to declare both a class and a companion object for each strong enum
* Strong enums do not have to be static any longer
* * Added scope protections to ChiselEnum.Value so that users cannot call it
outside of a ChiselEnum definition
* Renamed ChiselEnum.Value type to ChiselEnum.Type so that we can give
it a companion object just like UInt and Bool do
* * Moved strong enums into experimental package
* Non-literal UInts can now be cast to enums with apply() rather than
fromBits()
* Reduced code-duplication by moving some functions from EnumType and
Bits to Element
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* Modify noenq to set the input wires to DontCare.
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This places all do_* methods (and two unary methods in SInt and FixedPoint
that act like do_* methods) inside the ScalaDoc group
"SourceInfoTransformMacro". Classes/objects which need information about
this group have an additional bare trait mixed in, `SourceInfoDoc`, that
provides information about the group and its priority.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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* Ability to load memories at simulation startup
* first pass
* create annotation
* create skeleton Transform
* Work in progress
Building out transform and pass now
* Support for LoadMemory annotation
* Creates chisel and firrtl LoadMemory annotations
* LoadMemoryTransform converts annotation into BlackBox InLine
* Simple test that verilog bound modules get created.
* Support for LoadMemory annotation
* Supports Bundled/multi-field memories
* more tests
* support for `$readmemh` and `$readmemb`
* warns if suffix used in file specification.
* Support for LoadMemory annotation
* Use standard chisel annotation idiom
* Support for LoadMemory annotation
* Fixes for @seldridge nits and super-nits
* Support for LoadMemory annotation
- transform now only runs if emitter is an instance of VerilogEmitter
- suffixes on memory text files are now respected
- if suffix exists and memory is aggregate, aggregate sub-fields will now be inserted before suffix
- every bind module created gets a unique number
- this is required when multiple loaded memories appear in a module
- this should be generalized for other uses of binding modules
* Support for LoadMemory annotation
- remove un-needed suffix test
* Support for LoadMemory annotation
- remove instance walk, now just processes each module
* Support for LoadMemory annotation
- Move LoadMemoryTransformation into Firrtl for treadle to access it.
* Support for LoadMemory annotation
- One more bug in suffix handling has been eliminated
* Support for LoadMemory annotation
- remove unused findModule per jackkoenig
- fixed complex test, bad filename edge case
* Support for LoadMemory annotation
- changed to not use intellij style column alignment for : declarations
* Load memory from file
Fixes based on @jkoenig review
- remove unused BindPrefixFactory
- Moved code from CreateBindableMemoryLoaders into to LoadMemoryTransfrom
- Made map to find relevant memory annotations faster
- Made map to find modules referenced by annotations faster
- Made things private that should be private
- DefAnnotatedMemorys are no longer referenced, shouldn't be found here.
- println of error changed to failed
* Loading memories from files
- Many changes based on review
- move stuff into experimental
- clean up annotation manipulation
- manage tests better
- use more standard practices for transform
* Loading memories from files
- More review changes
- Move doc from annotation to the object apply method that generates the annotation
- Make scalastyle directives more specific
- Use more efficient collect to generate name to module map
- Made lines obey style length limit
- a couple of cleanups of imports in tests
- removed some commented out code
- optimized checking for lines using .exists
- use _ for unused variable in match
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