| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2016-09-22 | Update rest of docs | ducky | |
| 2016-09-21 | Improved scaladoc in utils and friends | ducky | |
| 2016-09-21 | Make implicit clock name consistent (#288) | Andrew Waterman | |
| In the Chisel frontend, the implicit clock is named clock, but in the generated FIRRTL, it is named clk. There is no reason for this discrepancy, and yet fixing it is painful, as it will break test harnesses. Better to take the pain now than later. Resolves #258. | |||
| 2016-09-15 | Decoupled: cast DecoupledIO to IrrevocableIO as an input (#280) | Wesley W. Terpstra | |
| 2016-09-13 | Bugfix: actually pass flow parameter from Queue factory to Queue module ↵ | Henry Cook | |
| constructor | |||
| 2016-09-08 | Add IrrevocableIO alternative to DecoupledIO (#274) | Henry Cook | |
| Add IrrevocableIO subclass of DecoupledIO that promises not to change .bits on a cycle after .valid is high and .ready is low | |||
| 2016-09-07 | Fix bug in Printable FullName of submodule port | jackkoenig | |
| Printable was using HasId.instanceName to get full names of Chisel nodes. instanceName uses the parent module of the HasId to get the Component to use in calling fullName on the underlying Ref. Unfortunately this means that any reference to a port of a instance will leave off the instance name. Fixing this required the following: - Add Component argument to Printable.unpack so that we can call Arg.fullName directly in the Printable - Pass the currently emitting module as the Component to Printable.unpack in the Emitter - Remove ability to create FullName Printables from Modules since the Module name is not known until after the printf is already emitted This commit also updates the PrintableSpec test to check that FullName and Decimal printing work on ports of instances | |||
| 2016-09-07 | Add Printable (#270) | Jack Koenig | |
| Printable is a new type that changes how printing of Chisel types is represented It uses an ordered collection rather than a format string and specifiers Features: - Custom String Interpolator for Scala-like printf - String-like manipulation of "hardware strings" for custom pretty-printing - Default pretty-printing for Chisel data types | |||
| 2016-08-25 | fix a bug in setModName | Donggyu Kim | |
| 2016-08-21 | provides signal name methods for firrtl annotation and chisel testers | Donggyu Kim | |
| * signalName: returns the chirrtl name of the signal * pathName: returns the full path name of the signal from the top module * parentPathName: returns the full path of the signal's parent module instance from the top module * parentModName: returns the signal's parent **module(not instance)** name. | |||
| 2016-08-15 | Make "def width" a private API; expose isWidthKnown instead (#257) | Andrew Waterman | |
| * Make "def width" a private API; expose isWidthKnown instead Resolves #256. Since width was used to determine whether getWidth would succeed, I added def isWidthKnown: Boolean but another option would be to expose something like def widthOption: Option[Int] ...thoughts? * Document getWidth/isWidthKnown * Add widthOption for more idiomatic Scala manipulation of widths | |||
| 2016-08-09 | Support Module name overrides with "override def desiredName" | Andrew Waterman | |
| The API allowed this before, but not safely, as users could create name conflicts. This exposes the pre-deduplication/sanitization naming API, and closes the other one. | |||
| 2016-08-09 | counter(inc,n) example should reflect actual use (#252) | Colin Schmidt | |
| 2016-07-31 | Remove deprecated FileSystemUtilities | Andrew Waterman | |
| This has been deprecated for a long time now (and really shouldn't have existed to begin with). | |||
| 2016-07-31 | Fix two deprecation warnings | Andrew Waterman | |
| 2016-07-11 | bitpat should keep the width of uint (#232) | Donggyu | |
| 2016-07-07 | Improve QoR for Log2 | Andrew Waterman | |
| For reasonable circuit delay, need to divide & conquer. | |||
| 2016-07-07 | Improve Fill code generation | Andrew Waterman | |
| 2016-07-07 | Correct erroneous Log2 documentation | Andrew Waterman | |
| 2016-07-07 | Avoid needlessly creating Vecs | Andrew Waterman | |
| 2016-06-28 | Merge branch 'master' into renamechisel3 | Jim Lawson | |
| 2016-06-27 | Guard firrtl stop, fixing pipelined reset | Andrew Waterman | |
| 2016-06-24 | Merge branch 'master' into renamechisel3 | Jim Lawson | |
| 2016-06-23 | Expose FIRRTL stop construct | Andrew Waterman | |
| 2016-06-22 | Merge branch 'master' into renamechisel3 | Jim Lawson | |
| 2016-06-20 | make sure MuxCase and MuxLookup can take all subclasses of Data (#222) | Howard Mao | |
| 2016-06-20 | Rename "package", "import", and explicit references to "chisel3". | Jim Lawson | |
| 2016-06-20 | Rename chisel3 package. | Jim Lawson | |
| 2016-06-08 | Move deprecated debug into compatibility | ducky | |
| 2016-06-08 | Package split chisel core | ducky | |
| 2016-06-08 | Move chisel/... to chisel/core/..., make chisel/compatibility ↵ | ducky | |
| package/folder, move more things into utils | |||
| 2016-06-08 | Move utils into utils | ducky | |
| 2016-06-08 | Add implicit xToLiteral, add Element, use internal package object | ducky | |
| 2016-06-08 | Rename packages to lowercase chisel, add compatibility layer | ducky | |
| 2016-05-31 | Remove unsafe implicit conversions from BitPat | ducky | |
| 2016-05-31 | Move BitPat out of core/frontend, add implicit conversion | Ducky | |
| 2016-05-26 | Fix type constraint on PriorityMux | Andrew Waterman | |
| 2016-05-20 | Merge pull request #186 from ucb-bar/sloc_impl | Richard Lin | |
| Source locators | |||
| 2016-05-20 | Implementation of source locators | ducky | |
| 2016-05-20 | Update BackendCompilationUtilities.verilogToCpp to specify top-module | jackkoenig | |
| This prevents Verilator from erroring when it cannot determine the top-module. It also changes the PRINTF_COND guard to correctly use the top-level reset instead of just the top of the Chisel-generated code. | |||
| 2016-05-12 | remove Tester.scala because chiselMain is now implemented in the ↵ | Danny | |
| chisel-testers repo | |||
| 2016-05-11 | RegNext and RegInit should match Reg(next=) and Reg(init=) | Andrew Waterman | |
| 2016-05-10 | Move emit out of IR | ducky | |
| 2016-05-09 | remove vpi source files | Donggyu Kim | |
| 2016-05-09 | fix width inference in enum | Donggyu Kim | |
| 2016-05-09 | get -> getOrElse | Donggyu Kim | |
| 2016-05-05 | Move Chisel API into separate chiselFrontend compilation unit in preparation ↵ | ducky | |
| for source locator macros | |||
| 2016-05-04 | Remove dependences from Chisel core on Chisel utils | Andrew Waterman | |
| Partially resolves #164 | |||
| 2016-05-04 | Support writing literals like 1.U or -1.S | Andrew Waterman | |
| 2016-05-04 | clock|reset to _clock|_reset, added explanatory comment | Stephen Twigg | |
| @aswaterman closes #156 | |||
