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2021-08-21Update ChiselStage.scala (#2082)Ruige Lee
There might be some "@"?
2021-08-18Revert "remove DefRegInit, change DefReg API with option definition. ↵Jack Koenig
(#1944)" (#2080) This reverts commit ed894c61474c8bc73761a6c360ef9d14505d853b.
2021-08-17remove DefRegInit, change DefReg API with option definition. (#1944)Jiuyang Liu
* remove DefRegInit, change DefReg API with option defination. * add error message * use Option[RegInitIR]. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-08-12Add DataView (#1955)Jack Koenig
DataView is a mechanism for "viewing" Scala objects as a subtype of `Data`. Often, this is useful for viewing one subtype of `Data`, as another. One can think about a DataView as a cross between a customizable cast and an untagged union. A DataView has a Target type `T`, and a View type `V`. DataView requires that an implementation of `DataProduct` is available for Target types. DataProduct is a type class that provides a way to iterate on `Data` children of objects of implementing types. If a DataView is provided for a type T to a type V, then the function .viewAs[V] (of type T => V) is available. The object (of type T) returned by .viewAs is called a "View" and can be used as both an rvalue and an lvalue. Unlike when using an .asTypeOf cast, connecting to a "View" will connect to the associated field or fields of the underlying Target. DataView also enables .viewAsSupertype which is available for viewing Bundles as a parent Bundle type. It is similar to .viewAs but requires a prototype object of the Target type which will be cloned in order to create the returned View. .viewAsSupertype maps between the corresponding fields of the parent and child Bundle types.
2021-08-12Pass truth table to espresso using stdin instead of temp fileBoyang Han
2021-08-03Added flush capability to Queue (#2030)anniej-sifive
Co-authored-by: Megan Wachs <megan@sifive.com> Co-authored-by: Deborah Soung <debs@sifive.com>
2021-07-14Espresso Decoder (#1964)Jiuyang Liu
Co-authored-by: Haoran Yuan <sinofp@tuta.io> Co-authored-by: Boyang Han <yqszxx@gmail.com>
2021-07-06Make printf return BaseSim subclass so it can be named/annotated (#1992)Deborah Soung
2021-06-29Change behavior of aop.Select to not include CloneModuleAsRecordJack Koenig
Previously, CloneModuleAsRecord clones would result in the same BaseModule object coming up multiple times when using APIs like .instances, .collectDeep, and .getDeep. This was not the intended behavior and can lead to very subtle bugs.
2021-06-29Restore aop.Select behavior for CloneModuleAsRecordJack Koenig
2021-06-24create and extend annotatable BaseSim class for verification nodes (#1968)Deborah Soung
* prototype annotating verif constructs * switch to final class * name emissions * moving BaseSim to experimental * adding name tests * fixing quotation escapes * emitting names, but everything has a default name * only name things with provided/suggested names * name every BaseSim node * removing msg, unused imports * fixing file exist calls
2021-06-16getVerilog in Chisel3 (#1921)Martin Schoeberl
2021-06-16Add computational complexity analysisBoyang Han
2021-06-16Refactor to a more `scala` formBoyang Han
2021-06-16Merge minimized table before return as a TruthTableBoyang Han
2021-06-16implement QMC.Boyang Han
2021-06-16Apply Jack's Review Jiuyang Liu
1. `TruthTable` is final now. 2. add return type for `TruthTable` Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-06-16add documentation for DecodeTableAnnotation.Jiuyang Liu
2021-06-16remove all timeouts by review.Jiuyang Liu
2021-06-16async decoder with 5 seconds timeout.Jiuyang Liu
2021-06-16add a simple decoder API.Jiuyang Liu
2021-06-16implement abstract Minimizer as a general API.Jiuyang Liu
2021-06-16fix for 2.13Jiuyang Liu
2021-06-16TruthTable can merge same inputs now.Jiuyang Liu
2021-06-16implement DecodeTableAnnotation for decode table caching.Jiuyang Liu
2021-06-16implement TruthTable to represent a decode table.Jiuyang Liu
2021-06-10Stop Emitting BlackBoxResourceAnno (#1954)Schuyler Eldridge
* Change HasBlackBoxResource to Resolve Resources Change HasBlackBoxResource to resolve resources immediately and emit BlackBoxInlineAnno instead of a BlackBoxResourceAnno. This removes the need for a FIRRTL compiler to grok the Java Resource API in order to handle BlackBoxResourceAnno. Emit BlackBoxInlineAnno from HasExtModuleResource instead of BlackBoxResourceAnno. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-05-25throw exception if BitPat width is 0 (#1920)Jiuyang Liu
* spot a bug when BitPat width is 0 * fix #1919 Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-05-20Implement PLA (#1912)Jiuyang Liu
* implement pla * implement test for pla * implement inverter matrix of PLA generator * fix for review. Co-authored-by: Boyang Han <yqszxx@gmail.com>
2021-05-10implement equal to BitPat. (#1867)Jiuyang Liu
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-05-09Fix ShiftRegister with 0 delay. (#1903)Jiuyang Liu
* Add test to check ShiftRegister(s) with delay is 0. This should break ShiftRegister(x, 0) since last is not exist in a empty Seq. Originally, test only test 1 to 4, which missed a potential bug from #1723. * Fix ShiftRegister with 0 delay. if ShiftRegisters is empty, java will complain: ``` java.util.NoSuchElementException scala.collection.LinearSeqOptimized.last(LinearSeqOptimized.scala:150) ``` This fix this issue and return `in` directly when ShiftRegister size is 0. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-05-06add ShiftRegisters to expose register inside ShiftRegister. (#1723)Jiuyang Liu
* add ShiftRegisters to expose register inside ShiftRegister. * use Seq.iter for oneline implementation.
2021-05-05Remove chisel3.stage.phases.DriverCompatibility (#1772)Schuyler Eldridge
2021-04-30add helper function to convert chirrtl to firrtl. (#1854)Jiuyang Liu
* add convert(chirrtl: cir.Circuit): fir.Circuit to convert chirrtl to firrtl. * add scaladoc. * add test. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-04-29Scala 2.13 support (#1751)Jack Koenig
2021-04-21fixing context bug (#1874)Deborah Soung
2021-03-18Add toString method to BitPat (#1819)Boyang Han
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-03-11Import memory files inline for Verilog generation (#1805)Carlos Eduardo
This annotation adds memory import with inline generation for the emmiter. Supports both readmemh and readmemb statements based on argument.
2021-03-01Fix conversions between DecoupledIO and IrrevocableIO (#1781)Jerry Zhao
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-02-26Expose AnnotationSeq to Module. (#1731)Jiuyang Liu
2021-02-11Fix stack trace trimming across Driver/ChiselStage (#1771)Schuyler Eldridge
* Handle MemTypeBinding in Analog Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> * Fix stack trace trimming across ChiselStage Fix bug in stack trace trimming behavior. Now, the following is what happens: 1. The Builder, if catching accumulated errors, will now throw a ChiselException with a Scala-trimmed Stack trace. Previously, this would throw the full excpetion. 2. The Elaborate phase handles stack trace trimming. By default, any Throwable thrown during elaboration will have its stack trace *mutably* trimmed and is rethrown. A logger.error is printed stating that there was an error during elaboration and how the user can turn on the full stack trace. If the --full-stacktrace option is on, then the Throwable is not caught and only the first logger.error (saying that elaboration failed) will be printed. 3. ChiselStage (the class), ChiselStage$ (the object), and ChiselMain all inherit the behavior of (2). Mutable stack trace trimming behavior is moved into an implicit class (previously this was defined on ChiselException only) so this can be applied to any Throwable. No StageErrors are now thrown anymore. However, StageErrors may still be caught by ChiselMain (since it is a StageMain). Testing is added for ChiselMain, ChiselStage, and ChiselStage$ to test all this behavior. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-02-08Parametrized Mem- & SyncReadMem-based implementation of the Queue class (#1740)Vladimir Milovanović
* Added SyncReadMem-based implementation of the Queue class * Rework of the parametrized Queue class SyncReadMem-based implementation * Modification of the parametrized Queue class SyncReadMem-based implementation * Limiting the visibility of the read address for SyncReadMem-based Queue Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-02-03Remove Deprecated APIs (#1730)Jiuyang Liu
2021-01-27Fix some typo and using foreach instead of map in BoringUtils (#1755)SoyaOhnishi
If a method passed to higher function does not return any value, it is prefer to use `foreach` instead of `map`. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-01-21Fold Chisel.CompatibilityModule into chisel3.internal.LegacyModuleJack Koenig
2021-01-21Remove val ioJack Koenig
Chisel projects no longer need -Xsource:2.11 when compiling with Scala 2.12. Autowrapping of "val io" for compatibility mode Modules is now implemented using reflection instead of calling the virtual method. Also move Chisel.BlackBox to new chisel3.internal.LegacyBlackBox
2021-01-21Rename MultiIOModule to ModuleJack Koenig
2020-11-16Improve source locators for switch statements. (#1669)Daniel Kasza
* Improve source locators for switch statements.
2020-11-02Bugfix - adding external modules was broken (#1649)Adam Izraelevitz
2020-10-26Bugfix - module name collision for injecting aspect (#1635)Adam Izraelevitz
* Bugfix - module name collision for injecting aspect * Fixed mechanism to avoid module name collisions * Added comments for reviewer feedback Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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