| Age | Commit message (Collapse) | Author |
|---|
|
|
|
|
|
|
|
Also restrict black boxes to not allow hardware inside of them since it was
being silently dropped anyway.
Resolves #289
|
|
Workaround for:
http://www.veripool.org/issues/1101-Verilator-Fix-SmallName-for-ParamTypeDType
|
|
Also, remove no-longer-special case for n=1.
|
|
|
|
|
|
* FixedPoint number support for chisel3
FixedPoint numbers have a width and a binary position
Either, neither or both maybe inferred.
Firrtl will convert these to SInts during lowering passes
* Fixes based on Jack's comments on PR #328
* Add experimental warning to FixedPoint class and object
* Fixed comment per Adam's comment on PR #328
|
|
Add a cloneType method to QueueIO
|
|
This causes Verilator tests to compile faster and use less memory
|
|
|
|
Provide support for chisel options
Provide support for firrtl options when called as part of chisel compile
provide command line support the above options via scopt
provide and execution result class that can be used when chisel3 is part
of some externally controlled toolchain
|
|
Candidate fix for #245
|
|
|
|
This reverts commit 10f170110cd00e7e5e0b428c0490594dac4db225.
|
|
|
|
|
|
This reverts commit 3ea7faaad0c3e349c531fabc8a75440337bdc235, reversing
changes made to 7aea39d4deac62d5477904f4bf4381c3482c41d0.
Update chisel-testers before commiting this change (deleting EnqIO/DeqIO).
|
|
|
|
|
|
|
|
|
|
|
|
Merge with master and support checking for failure with an explicit assertion message.
|
|
This was originally mixed in with #199, Add Assert Data.
|
|
|
|
|
|
|
|
|
|
Massage CompileOption names in an attempt to preserve default (Strict) CompileOptions in the absence of explicit imports.
NOTE: Since the default is now strict, we may encounter errors when we generate connections for clients (i.e., in Vec.do_apply() when we wire up a sequence).
We should really thread the CompileOptions through the macro system so the client's implicits are used.
|
|
firrtlDirection should only be used for emitting firrtl. Any checks on the actual direction should use the bound Direction `dir`.
|
|
|
|
|
|
|
|
|
|
In the Chisel frontend, the implicit clock is named clock, but in the
generated FIRRTL, it is named clk. There is no reason for this
discrepancy, and yet fixing it is painful, as it will break test harnesses.
Better to take the pain now than later.
Resolves #258.
|
|
o explain why this merge is necessary,
|
|
|
|
|
|
|
|
|
|
constructor
|
|
|
|
Add IrrevocableIO subclass of DecoupledIO that promises not to change .bits on a cycle after .valid is high and .ready is low
|
|
Printable was using HasId.instanceName to get full names of Chisel nodes.
instanceName uses the parent module of the HasId to get the Component to use in
calling fullName on the underlying Ref. Unfortunately this means that any
reference to a port of a instance will leave off the instance name. Fixing this
required the following:
- Add Component argument to Printable.unpack so that we can call Arg.fullName
directly in the Printable
- Pass the currently emitting module as the Component to Printable.unpack in
the Emitter
- Remove ability to create FullName Printables from Modules since the Module
name is not known until after the printf is already emitted
This commit also updates the PrintableSpec test to check that FullName and
Decimal printing work on ports of instances
|
|
Printable is a new type that changes how printing of Chisel types is represented
It uses an ordered collection rather than a format string and specifiers
Features:
- Custom String Interpolator for Scala-like printf
- String-like manipulation of "hardware strings" for custom pretty-printing
- Default pretty-printing for Chisel data types
|
|
|
|
Eliminate builder compileOptions.
|
|
|
