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* Add support for readUnderWrite to SyncReadMem
* Add write collision behavior test to MemorySpec
* Update constant names
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* Change when thunks return type to Any
Changes the type of the thunk for when and WhenContext methods from
call-by-name Unit to call-by-name Any. This prevents a
warning (-Ywarn-value-discard) where a when thunk is returning
something other than Unit that is then discarded, e.g., another
WhenContext.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
* Change switch thunk return to type to Any
Changes the type of switch thunks from call-by-name Unit to
call-by-name Any. This prevents a warning (-Ywarn-value-discard) when
the internals of a switch block return something other than Unit which
is then discarded.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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The BitPat.parse factory though did not remove these from the returned count.
This fixes that adds whitespace and underscores to the unit tests
This is an updated vesion of Chisel PR #1069
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This removes a dead line where a WriteEmitted phase is constructed.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This reverts commit 85fe90d5b7ed4e1101b0b3959a1d362eb93915ac.
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* Use macro to materialize CompileOptions in Chisel._
This switches from using an implicit val that required awkward
suppression (as illustrated in CompileOptionsSpec) to allowing
overriding in the same way as done in "import chisel3._" via the
creation of an implicit val in lexical scope.
* Deprecate Chisel.defaultCompileOptions
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This modifies MuxLookup to not use the 'default' mapping argument if a
"full" mapping is provided. A "full" mapping enumerates all possible
cases for a 'key' argument of a known size. This will check literal
values to ensure exhaustiveness holds.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
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This enables users to use the nice run method of `ChiselStage` with their own set of phases.
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This fixes a bug where internal boring using BoringUtils.bore would
fail because it was using instanceName which cannot be called before
the module closes. Previously, this meant that BoringUtils.bore would
work for boring instances (which are closed in a parent), but not for
boring signals in the current, unclosed module.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Plan to be released with 3.3.
Breaks experimental Range API.
Adds new Interval type and associated support.
This commit adds the following:
- Renamed Range to IntervalRange to avoid name collision with scala Range
- Changed RangeTransform macro to Return an IntervalRange
- Improved error messages on missing comma or decimal
- Added notational support for binary point
- Some formatting cleanup also
- SIntFactory
- Change to use IntervalRange API
- UIntFactory
- UInt from range has custom width computation
- It does not need to deal with lowerbound extending bit requirements
- Code to handle special case of range"[0,0]" to have a width of 1
- IR.scala
- Removed Bound and other constraint code that was duplicating firrtl stuff
- Added new RangeType
- Added IntervalRange class and object
- RangeSpec
- modified just a bit to handle notational differences
- previous range interpolator returned tuple now returns IntervalRange
- Add IntervalType to emitter
- Added IntervalSpec with many tests
- Added ScalaIntervalSimulatorSpec which tests golden model for Interval
- Added ScalaIntervalSimulator which is a golden model for Interval
- This gold may not have been polished to a high sheen
- Add IntervalLit cases to Converter
- Add Interval PrimOps to IR
- asInterval, wrap, squz, clip, setp, decp, incp
- Add IntervalLit class to IR
- Add Interval to MonoConnect
- Add Interval Type to Bits (in experimental package)
- add conversions to Interval from other types
- Add Interval clone stuff to Data
- Add Literal creation helpers to chisel3 package
- these may move to experimental if I can figure that out
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FIRRTL barfs on negative and zero-sized memories
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* Move dontTouch out of experimental package.
* Move RawModule, MultiIOModule out of experimental.
* Respond to comments - Move LagacyModule from experimental to internal.
*NOTE*: At some point, these module definitions (especially those in separate packages) should be moved to individual files at the appropriate location in the source tree. The current organization is purely to support comparison with prior versions.
* Fix up a few more imports.
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Migrate Driver to use a PhaseManager to internally resolve Phase
ordering. This requires the use of an identity node to adequately
describe the necessary prerequisite/dependents.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
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Modifies ChiselStage to use a PhaseManager for Phase ordering.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
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Adds new AsyncReset and "abstract" Reset types. Reset is inferred
in FIRRTL to be either AsyncReset or Bool. The "reset type" of a
register is set by the type of its reset signal:
val asyncReset: AsyncReset = IO(Input(AsyncReset()))
val syncReset: Bool = IO(Input(Bool()))
val abstractReset: Reset = IO(Input(Reset()))
val asyncReg = withReset(asyncReset) { RegInit(0.U) }
val syncReg = withReset(syncReset) { RegInit(0.U) }
val inferredReg = withReset(abstractReset) { RegInit(0.U) }
AsyncReset can be cast to and from Bool. Whereas synchronous reset is
equivalent to a mux in front of a flip-flop and thus can be driven by
logic, asynchronous reset requires that the reset value is a constant.
This is checked in FIRRTL.
Inference of the concrete type of a Reset occurs based on the type the
Reset's drivers. This inference is very simple, it is simple forward propagation
of the type, but it allows for writing blocks and modules that are agnostic
to the reset type. In particular, the implicit `reset` value in MultiIOModule
and thus Module is now concretely an instance of Reset and thus will be
inferred in FIRRTL.
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Added Aspects to Chisel, enabling a mechanism for dependency injection to hardware modules.
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Muxes and resets are only isomorphic with synchronous reset. Use a reset
instead of a conditional to make this async-reset-safe.
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This renames all *FactoryBase traits to *Factory, removes
transparent *Factory objects, and propagates this flattened hierarchy
throughout the codebase.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Anything removed by this that is used by the compatibility layer is
migrated to the compatibility layer.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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* Add width utility functions to avoid incorrect usage of bare log2Ceil().
* Respond to comments:
Remove apply(Data) method.
Change name(s) to signedBitLength, unsignedBitLength.
* Respond to comments - don't be lazy.
Independently calculate the bit length to verify correct operation.
* Respond to comments - return in.bitLength - 0 (not 1) for 0
* Respond to comments - update wdith for signed 0; add explicit tests.
* Add comment expressing zero width wire assumption.
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* Added documentation to Decoupled, Conditionals, Counter
* Fixed private Counter class error
* Move Counter class deprecation and re-definition into util package object.
* Revert "Move Counter class deprecation and re-definition into util package object."
This reverts commit f61bdddf7051522363e1d203fcd46b512047c87d.
* Restore the old Counter definition and address this in a separate PR.
We can move the deprecation warning and the type definition into the util package object (see f61bdddf7051522363e1d203fcd46b512047c87d), but then we fail tests using Counter with a `ScalaReflectionException` in Aggregate.scala:779 (in def cloneType) when:
`Some(mirror.reflect(this).symbol)` generates `type Counter is not a class`.
* Made @ducky64 change to Counter doc
Used to generate an inline (logic directly in the containing Module, no internal Module is created) hardware counter.
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This converts the original chisel3.Driver to use
chisel3.stage.ChiselStage. This is implemented in the following way:
1. ExecutionOptions are converted to an AnnotationSeq
2. The AnnotationSeq is preprocessed using phases contained in the
Chisel DriverCompatibility objects. One of these *disables* the
execution of FirrtlStage by ChiselStage.
3. ChiselStage runs on the preprocessed AnnotationSeq
4. The input ExecutionOptionsManager is mutated based on the output
of ChiselStage.
5. The FIRRTL stage is re-enabled if it's supposed to run and
selected FIRRTL DriverCompatibility phases run.
6. FirrtlStage runs
7. The output AnnotationSeq is "viewed" as a ChiselExecutionResult
This modifies the original DriverSpec to make it more verbose with the
addition of info statements. The functionality of the DriverSpec is
unmodified.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Adds a method to enable conversion from ChiselExecutionOptions back to
an AnnotationSeq.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This includes phases necessary to provide backwards compatibility with
the old Chisel3 Driver. These are placed in a DriverCompatibility
object inside chisel3.stage.phases. The following four phases are
included:
- AddImplicitOutputFile (from a TopNameAnnotation)
- AddImplicitOutputAnnotationFile phase
- DisableFirrtlStage (to disable ChiselStage running FirrtlStage)
- MutateOptionsManager (to update options after ChiselStage)
- ReEnableFirrtlStage (to renable FirrtlStage if needed)
Additionally, this adds a view of a ChiselExecutionResult for
providing the legacy return type of the Chisel Driver.
Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-Authored-By: chick <chick@qrhino.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This adds ChiselStage, a reimplementation of chisel3.Driver as a
firrtl.options.Stage. This is simplistically described as a pipeline
of Phases.
Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-Authored-By: chick <chick@qrhino.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
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Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-Authored-By: chick <chick@qrhino.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This adds an Emitter Phase that writes a ChiselCircuitAnnotation to
a file if a ChiselOutputFileAnnotation is present.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This coalesces three distinct operations into one Convert Phase:
1. Chisel Circuit to FIRRTL Circuit (CHIRRTL) conversion
2. Conversion of Chisel Annotations to FIRRTL Annotations
3. Generation of RunFirrtlTransformAnnotations
Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-Authored-By: chick <chick@qrhino.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This adds an Elaborate Phase that expands ChiselGeneratorAnnotations
into ChiselCircuitAnnotations and deletes the original.
Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-Authored-By: chick <chick@qrhino.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-Authored-By: chick <chick@qrhino.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-Authored-By: chick <chick@qrhino.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This adds the following FIRRTL Annotations to Chisel:
- NoRunFirrtlCompilerAnnotation
- PrintFullStackTraceAnnotation
- ChiselGeneratorAnnotation
- ChiselCircuitAnnotation
- ChiselOutputFileAnnotation
This includes tests for ChiselGeneratorAnnotation as this Annotation
is able to be constructed from a String and to elaborate itself.
Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-Authored-By: chick <chick@qrhino.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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* Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3
and deal with the subsequent fallout.
* Move Aggregate, Clock, Mem, Printf, Reg
* Move almost all chisel3.core definitions to chisel3 or chisel3.experimental
* Revive core package object to provide aliases for moved definitions.
* Cleanup package definitions; eliminate ambiguous implicits
* Move more definitions to experimental.
Extract BaseModule, DataMirror, ExtModule, IO into their own files.
* Put BitPat back in chisel3.util
* More experimental motion - avoid multiple import definitions.
* Add experimental.FixedPoint alias
* Add EnumType definition to core package.
Update deprecated messages to refer to correct object
* Move FixedPoint into the experimental package (but keep it in Bits.scala).
* Add missing implicits to core/package - compatibility
* Cleanup: update ScalaDoc references; remove unused imports
* Add Reset alias to core/package
* Use common 3.2 version in deprecation warning
* Move Binding from core to internal.
* Optimize imports.
* Repair IntelliJ's overly cleanliness.
* Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3
and deal with the subsequent fallout.
Move Aggregate, Clock, Mem, Printf, Reg
Move almost all chisel3.core definitions to chisel3 or chisel3.experimental
Revive core package object to provide aliases for moved definitions.
Cleanup package definitions; eliminate ambiguous implicits
Move more definitions to experimental.
Extract BaseModule, DataMirror, ExtModule, IO into their own files.
Add EnumType definition to core package.
Update deprecated messages to refer to correct object
Move FixedPoint into the experimental package (but keep it in Bits.scala).
Add missing implicits to core/package - compatibility
Cleanup: update ScalaDoc references; remove unused imports
Use common 3.2 version in deprecation warning
Move Binding from core to internal.
* Change == to reference equality (eq) in Data print (#1044)
* Remove @chiselName from MixedVec (#1045)
* Fix enum annotations (#936)
* Turned off strong enum annotations because they weren't working with Vec
indexes
* Add new EnumVecAnnotation for vecs of enums and vecs of bundles with
enum fields
* Changed Clock's width parameter back to a fixed constant value of 1
* Fixed enum annotations for Vecs of Bundles which contain enum elements
* Fixed usage of "when/otherwise" to use consistent style
* Add Record to type hierarchy documentation
* Undeprecate isLit (#1048)
* move doNotDedup to experimental (#1008)
* Aggregate coverage - aggregate tests but not publishing (#1040)
Discover a working combination of aggregate usage to enable coverage of subproject testing but publish a single Jar.
Use "scalastyle-test-config.xml" for scalastyle config in tests.
Enable "_" in method names and accept method names ending in "_=".
Re-sync scalastyle-test-config.xml with scalastyle-config.xml
This should finally fix #772.
* Check field referential equality in autoclonetype (#1047)
* Allow naming annotation to work outside builder context (#1051)
* Try to eliminate JVM hang due to static initialization deadlock (#1053)
* Make core.DontCare private to chisel3 (#1054)
Force clients to access 'DontCare' through the chisel3 package to ensure it's created as a chisel3 object and not a client object.
* Ignore empty aggregates elements when binding aggregate direction (#946)
Previously, including an empty aggregate in a Bundle would cause
a MixedDirectionAggregateException because it has no elements and thus
doesn't have a direction
* Add SampleElementBinding for Vec sample elements
* Add ActualDirection.Empty for bound empty aggregates
* Detect bundle aliasing (#1050)
* Implement connectFromBits in ChiselEnum (#1052)
This is necessary to use ChiselEnum in aggregates where things are
casted using .asTypeOf
* Optimize imports.
* Move Analog to experimental.
* More repackage cleanup - reduce differences with master.
* Cleanup chisel3 references.
* More chisel3 reference cleanup.
* Merge cleanup.
* Remove unused import
* Bump core deprecation to 3.3
* Move DontCare back into Data.scala inside package internal
* Re-indent experimental/internal package code
* Move code back to original files - facilitate comparison with other branches
* Some code motion, update imports, minimize master differences
Move exceptions up to chisel3 package object - they're part of the interface.
* More master diff minimization.
* Try to eliminate JVM hang due to static initialization deadlock (#1053)
* Ignore empty aggregates elements when binding aggregate direction (#946)
Previously, including an empty aggregate in a Bundle would cause
a MixedDirectionAggregateException because it has no elements and thus
doesn't have a direction
* Add SampleElementBinding for Vec sample elements
* Add ActualDirection.Empty for bound empty aggregates
* Implement connectFromBits in ChiselEnum (#1052)
This is necessary to use ChiselEnum in aggregates where things are
casted using .asTypeOf
* Move Analog to experimental.
More repackage cleanup - reduce differences with master.
Cleanup chisel3 references.
More chisel3 reference cleanup.
* Fix wrong directionality for Vec(Flipped())
Create Chisel IR Port() in a way that Converter is happy with.
Also add more extensive test suite for future-proofing.
Close #1063
* Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3
and deal with the subsequent fallout.
Move Aggregate, Clock, Mem, Printf, Reg
Move almost all chisel3.core definitions to chisel3 or chisel3.experimental
Revive core package object to provide aliases for moved definitions.
Cleanup package definitions; eliminate ambiguous implicits
Move more definitions to experimental.
Extract BaseModule, DataMirror, ExtModule, IO into their own files.
Put BitPat back in chisel3.util
More experimental motion - avoid multiple import definitions.
Add experimental.FixedPoint alias
Add EnumType definition to core package.
Update deprecated messages to refer to correct object
Move FixedPoint into the experimental package (but keep it in Bits.scala).
Add missing implicits to core/package - compatibility
Cleanup: update ScalaDoc references; remove unused imports
Add Reset alias to core/package
Use common 3.2 version in deprecation warning
Move Binding from core to internal.
Optimize imports.
Repair IntelliJ's overly cleanliness.
Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3
and deal with the subsequent fallout.
Move Aggregate, Clock, Mem, Printf, Reg
Move almost all chisel3.core definitions to chisel3 or chisel3.experimental
Revive core package object to provide aliases for moved definitions.
Cleanup package definitions; eliminate ambiguous implicits
Move more definitions to experimental.
Extract BaseModule, DataMirror, ExtModule, IO into their own files.
Add EnumType definition to core package.
Update deprecated messages to refer to correct object
Move FixedPoint into the experimental package (but keep it in Bits.scala).
Add missing implicits to core/package - compatibility
Cleanup: update ScalaDoc references; remove unused imports
Use common 3.2 version in deprecation warning
Move Binding from core to internal.
Optimize imports.
Merge cleanup.
Remove unused import
Bump core deprecation to 3.3
Move DontCare back into Data.scala inside package internal
Re-indent experimental/internal package code
Move code back to original files - facilitate comparison with other branches
Some code motion, update imports, minimize master differences
Move exceptions up to chisel3 package object - they're part of the interface.
More master diff minimization.
Fix minor discrepancies with repackagecore-testbed
* Remove redundant imports
As part of its import updating process, IntelliJ converted some import statements to `import package.{object, _}`. Is this intended to show an explicit dependency on `package.object` and a further dependency on `package` implicits? Unsure. Replace these with `import package._`
* Move the BaseModule object into the internal package.
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This moves the documentation for loadMemoryFromFile onto the object as
opposed to the apply method. This includes additional cleanup in terms
of fixing uses of "$", topical grammar/capitalization, and adding more
outbound links.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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