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path: root/src/main/scala/chisel3
AgeCommit message (Collapse)Author
2016-09-15Decoupled: cast DecoupledIO to IrrevocableIO as an input (#280)Wesley W. Terpstra
2016-09-13Bugfix: actually pass flow parameter from Queue factory to Queue module ↵Henry Cook
constructor
2016-09-08Add IrrevocableIO alternative to DecoupledIO (#274)Henry Cook
Add IrrevocableIO subclass of DecoupledIO that promises not to change .bits on a cycle after .valid is high and .ready is low
2016-09-07Fix bug in Printable FullName of submodule portjackkoenig
Printable was using HasId.instanceName to get full names of Chisel nodes. instanceName uses the parent module of the HasId to get the Component to use in calling fullName on the underlying Ref. Unfortunately this means that any reference to a port of a instance will leave off the instance name. Fixing this required the following: - Add Component argument to Printable.unpack so that we can call Arg.fullName directly in the Printable - Pass the currently emitting module as the Component to Printable.unpack in the Emitter - Remove ability to create FullName Printables from Modules since the Module name is not known until after the printf is already emitted This commit also updates the PrintableSpec test to check that FullName and Decimal printing work on ports of instances
2016-09-07Add Printable (#270)Jack Koenig
Printable is a new type that changes how printing of Chisel types is represented It uses an ordered collection rather than a format string and specifiers Features: - Custom String Interpolator for Scala-like printf - String-like manipulation of "hardware strings" for custom pretty-printing - Default pretty-printing for Chisel data types
2016-08-25fix a bug in setModNameDonggyu Kim
2016-08-21provides signal name methods for firrtl annotation and chisel testersDonggyu Kim
* signalName: returns the chirrtl name of the signal * pathName: returns the full path name of the signal from the top module * parentPathName: returns the full path of the signal's parent module instance from the top module * parentModName: returns the signal's parent **module(not instance)** name.
2016-08-15Make "def width" a private API; expose isWidthKnown instead (#257)Andrew Waterman
* Make "def width" a private API; expose isWidthKnown instead Resolves #256. Since width was used to determine whether getWidth would succeed, I added def isWidthKnown: Boolean but another option would be to expose something like def widthOption: Option[Int] ...thoughts? * Document getWidth/isWidthKnown * Add widthOption for more idiomatic Scala manipulation of widths
2016-08-09Support Module name overrides with "override def desiredName"Andrew Waterman
The API allowed this before, but not safely, as users could create name conflicts. This exposes the pre-deduplication/sanitization naming API, and closes the other one.
2016-08-09counter(inc,n) example should reflect actual use (#252)Colin Schmidt
2016-07-31Remove deprecated FileSystemUtilitiesAndrew Waterman
This has been deprecated for a long time now (and really shouldn't have existed to begin with).
2016-07-31Fix two deprecation warningsAndrew Waterman
2016-07-11bitpat should keep the width of uint (#232)Donggyu
2016-07-07Improve QoR for Log2Andrew Waterman
For reasonable circuit delay, need to divide & conquer.
2016-07-07Improve Fill code generationAndrew Waterman
2016-07-07Correct erroneous Log2 documentationAndrew Waterman
2016-07-07Avoid needlessly creating VecsAndrew Waterman
2016-06-28Merge branch 'master' into renamechisel3Jim Lawson
2016-06-24Merge branch 'master' into renamechisel3Jim Lawson
2016-06-22Merge branch 'master' into renamechisel3Jim Lawson
2016-06-20Rename "package", "import", and explicit references to "chisel3".Jim Lawson
2016-06-20Rename chisel3 package.Jim Lawson