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* Support for creating chisel annotations that are consumed by firrtl
Update annotation serialization in Driver
Add DiamondAnnotation Spec that illustrates how to do simple annotations
frontEnd must have dependency on firrtl
Add annotation method to Module
Circuit has extra optional parameter that is Seq of Annotations
In Builder add annotation buffer to DynamicContext to store annotations created in modules
Added explicit types on naming api methods to avoid type confusion
Because some names are not available until elaboration create intermediate ChiselAnnotation that
gets turned into a firrtl Annotation after elaboration
In execute pass firrtl text and annotation to firrtl are now passed in through optionManager, though
intermediate file .fir and .anno files are still created for inspection and/or later use
* Somehow missed ChiselAnnotation
* fixes for Jack's review of PR
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Add examples for utils, move examples from individual apply methods to class overview scaladoc
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(#387)
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Get rid of some cruft exposed in #373
This also allows Bits.fromtInt(...) to be removed. Yay!
All old APIs (with some new restrictions, rocket still works fine) are preserved without deprecation in Chisel._, aside from the non-compile-time-checkable Map[] enum constructor which probably should have been deprecated during chisel2. The Map[] enums have been removed from chisel3._ without deprecation.
The new restriction is that nodeType (legacy API) may only be of UInt type with unspecified width. Note that Bits() creates a UInt, and if you can't control the enum values, it makes little sense to specify a bitwidth.
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Remove modName from Module
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compatibility package object
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Also restrict black boxes to not allow hardware inside of them since it was
being silently dropped anyway.
Resolves #289
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Workaround for:
http://www.veripool.org/issues/1101-Verilator-Fix-SmallName-for-ParamTypeDType
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Also, remove no-longer-special case for n=1.
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* FixedPoint number support for chisel3
FixedPoint numbers have a width and a binary position
Either, neither or both maybe inferred.
Firrtl will convert these to SInts during lowering passes
* Fixes based on Jack's comments on PR #328
* Add experimental warning to FixedPoint class and object
* Fixed comment per Adam's comment on PR #328
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Add a cloneType method to QueueIO
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This causes Verilator tests to compile faster and use less memory
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Provide support for chisel options
Provide support for firrtl options when called as part of chisel compile
provide command line support the above options via scopt
provide and execution result class that can be used when chisel3 is part
of some externally controlled toolchain
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Candidate fix for #245
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This reverts commit 10f170110cd00e7e5e0b428c0490594dac4db225.
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This reverts commit 3ea7faaad0c3e349c531fabc8a75440337bdc235, reversing
changes made to 7aea39d4deac62d5477904f4bf4381c3482c41d0.
Update chisel-testers before commiting this change (deleting EnqIO/DeqIO).
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Merge with master and support checking for failure with an explicit assertion message.
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This was originally mixed in with #199, Add Assert Data.
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Massage CompileOption names in an attempt to preserve default (Strict) CompileOptions in the absence of explicit imports.
NOTE: Since the default is now strict, we may encounter errors when we generate connections for clients (i.e., in Vec.do_apply() when we wire up a sequence).
We should really thread the CompileOptions through the macro system so the client's implicits are used.
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