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path: root/src/main/scala/chisel3
AgeCommit message (Expand)Author
2021-08-23Emit .fir lazily, overcomes JVM 2 GiB String limitJack Koenig
2021-08-23Remove chisel3's own firrtl Emitter, use firrtl SerializerJack Koenig
2021-08-21Update ChiselStage.scala (#2082)Ruige Lee
2021-08-18Revert "remove DefRegInit, change DefReg API with option definition. (#1944)"...Jack Koenig
2021-08-17remove DefRegInit, change DefReg API with option definition. (#1944)Jiuyang Liu
2021-08-12Add DataView (#1955)Jack Koenig
2021-08-12Pass truth table to espresso using stdin instead of temp fileBoyang Han
2021-08-03Added flush capability to Queue (#2030)anniej-sifive
2021-07-14Espresso Decoder (#1964)Jiuyang Liu
2021-07-06Make printf return BaseSim subclass so it can be named/annotated (#1992)Deborah Soung
2021-06-29Change behavior of aop.Select to not include CloneModuleAsRecordJack Koenig
2021-06-29Restore aop.Select behavior for CloneModuleAsRecordJack Koenig
2021-06-24create and extend annotatable BaseSim class for verification nodes (#1968)Deborah Soung
2021-06-16getVerilog in Chisel3 (#1921)Martin Schoeberl
2021-06-16Add computational complexity analysisBoyang Han
2021-06-16Refactor to a more `scala` formBoyang Han
2021-06-16Merge minimized table before return as a TruthTableBoyang Han
2021-06-16implement QMC.Boyang Han
2021-06-16Apply Jack's Review Jiuyang Liu
2021-06-16add documentation for DecodeTableAnnotation.Jiuyang Liu
2021-06-16remove all timeouts by review.Jiuyang Liu
2021-06-16async decoder with 5 seconds timeout.Jiuyang Liu
2021-06-16add a simple decoder API.Jiuyang Liu
2021-06-16implement abstract Minimizer as a general API.Jiuyang Liu
2021-06-16fix for 2.13Jiuyang Liu
2021-06-16TruthTable can merge same inputs now.Jiuyang Liu
2021-06-16implement DecodeTableAnnotation for decode table caching.Jiuyang Liu
2021-06-16implement TruthTable to represent a decode table.Jiuyang Liu
2021-06-10Stop Emitting BlackBoxResourceAnno (#1954)Schuyler Eldridge
2021-05-25throw exception if BitPat width is 0 (#1920)Jiuyang Liu
2021-05-20Implement PLA (#1912)Jiuyang Liu
2021-05-10implement equal to BitPat. (#1867)Jiuyang Liu
2021-05-09Fix ShiftRegister with 0 delay. (#1903)Jiuyang Liu
2021-05-06add ShiftRegisters to expose register inside ShiftRegister. (#1723)Jiuyang Liu
2021-05-05Remove chisel3.stage.phases.DriverCompatibility (#1772)Schuyler Eldridge
2021-04-30add helper function to convert chirrtl to firrtl. (#1854)Jiuyang Liu
2021-04-29Scala 2.13 support (#1751)Jack Koenig
2021-04-21fixing context bug (#1874)Deborah Soung
2021-03-18Add toString method to BitPat (#1819)Boyang Han
2021-03-11Import memory files inline for Verilog generation (#1805)Carlos Eduardo
2021-03-01Fix conversions between DecoupledIO and IrrevocableIO (#1781)Jerry Zhao
2021-02-26Expose AnnotationSeq to Module. (#1731)Jiuyang Liu
2021-02-11Fix stack trace trimming across Driver/ChiselStage (#1771)Schuyler Eldridge
2021-02-08Parametrized Mem- & SyncReadMem-based implementation of the Queue class (#1740)Vladimir Milovanović
2021-02-03Remove Deprecated APIs (#1730)Jiuyang Liu
2021-01-27Fix some typo and using foreach instead of map in BoringUtils (#1755)SoyaOhnishi
2021-01-21Fold Chisel.CompatibilityModule into chisel3.internal.LegacyModuleJack Koenig
2021-01-21Remove val ioJack Koenig
2021-01-21Rename MultiIOModule to ModuleJack Koenig
2020-11-16Improve source locators for switch statements. (#1669)Daniel Kasza
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