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2022-08-02Remove remaining chiselNames (#2635) (#2656)mergify[bot]
(cherry picked from commit 8538269a14e0d5a1163298a79aa43b77a380aabc) Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
2022-07-28Implement DecoupledIO.map utility (#2646) (#2649)mergify[bot]
(cherry picked from commit b20df1d6cda03f6eef28ee480e0aade914c5face) Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
2022-07-21Deprecate chiselName and NoChiselNamePrefix trait (#2627) (#2633)mergify[bot]
Also remove all non-testing uses of chiselName. (cherry picked from commit 1c5d1b5317a0c9fe7ef9d15138065a817380a1e4) Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
2022-07-06Refactor TruthTable.apply and add factory method for Espresso (backport ↵mergify[bot]
#2612) (#2620) * Refactor TruthTable.apply and add factory method for Espresso (#2612) Improves performance of creating TruthTables by processing entire BitPats rather than individual bits. New TruthTable factory method enables constructing TruthTables with semantics of OR-ing output BitPats together rather than erroring when multiple terms have the same input BitPat. This alternative factory method matches semantics for the output format of Espresso. Co-authored-by: Megan Wachs <megan@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit 231f14e74f112a9f721e774561126b2bd1250039) # Conflicts: # src/main/scala/chisel3/util/BitPat.scala * Resolve backport conflicts Co-authored-by: Aditya Naik <91489422+adkian-sifive@users.noreply.github.com>
2022-07-06Implement trait for Chisel compiler to name arbitrary non-Data types (#2610) ↵mergify[bot]
(#2617) Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: Megan Wachs <megan@sifive.com> (cherry picked from commit 3ab34cddd8b87c22d5fc31020f10ddb2f1990d51) Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
2022-06-27Deprecate TransitName (backport #2603) (#2606)mergify[bot]
* Deprecate TransitName (#2603) * Deprecate TransitName * Add @nowarn macros to usages of TransitName in the repo Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit a0b05190e5303ec28a0c7abe645d81e9a72023ff) * Update src/main/scala/chisel3/util/Valid.scala * Update src/main/scala/chisel3/util/Valid.scala Co-authored-by: Megan Wachs <megan@sifive.com>
2022-06-11Micro-optimize BitPat.rawString (#2577) (#2578)mergify[bot]
BitPat.rawString is called a lot when decoding and is used for certain BitPat operations. We should use it less but this is at least a bandaid. (cherry picked from commit c11af20fe5b211ec72ba00f3ce0880d7933e566b) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-05-14Deprecate named arguments for methods moving to macros in 3.6 (#2530)Jack Koenig
These methods will start using def macros and since def macros do not supported named arguments this will be a source-incompatible change. This deprecation will warn users that they need to remove any uses of named arguments on these methods.
2022-03-25rm unused/deprecated BlackBoxResourceAnno import (#2458) (#2460)mergify[bot]
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> (cherry picked from commit 2c2d72ceaa494b6acc351ff4300dbb40d4a7d863) Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2022-02-15Make TruthTable accept unknown input width (#2387) (#2417)mergify[bot]
Widths are now padded to the maximum width of the inputs. Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit 546b4e13fe90ff09d24b63664c072d46c13c0c38) Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
2022-02-03FillInterleaved documentation: swap order of elements in Seq example (#2393) ↵mergify[bot]
(#2395) (cherry picked from commit 055a85298c46c6734880cd828af436adbded1d0a) Co-authored-by: John Ingalls <43973001+ingallsj@users.noreply.github.com>
2022-01-28Fix Decoder bug for constant 0 and DC (#2363) (#2371)mergify[bot]
* Fix the QMC bug for constant and dontcare output. * Fix the Espresso bug for constant and dontcare output. (cherry picked from commit 46b53320e9ec09fc26d63259f1821f4234640839) Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
2022-01-19util: add GrayCode (#2353) (#2354)mergify[bot]
(cherry picked from commit 91d7baa8e7162d736f46b6d4964b09016d2dd172) Co-authored-by: Kevin Laeufer <laeufer@cs.berkeley.edu>
2022-01-10Apply scalafmtJack Koenig
Command: sbt scalafmtAll
2021-12-16BitSet API (#2211)Jiuyang Liu
BitSet is a new experimental parent type for BitPat. It enables more complex operations on BitPats. Co-authored-by: Ocean Shen <shenao6626@gmail.com>
2021-12-15Refactor TruthTable to use Seq (#2217)Jiuyang Liu
This makes the resulting Verilog from decoding a TruthTable deterministic.
2021-12-09catch None.get in BitPat.apply(x: UInt): BitPat (#2276)Jiuyang Liu
Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-11-22add documentations to decoder. (#2254)Jiuyang Liu
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-11-17refactor Queue.hasFlush: Boolean to Queue.flush: Option[Bool]. (#2245)Jiuyang Liu
* refactor Queue.hasFlush: Boolean to Queue.flush: Option[Bool]. Using factory Queue(..., hasFlush = true) won't take effects, since in the Queue.apply API, Queue Module is not exposed, thus even user defines hasFlush = true, there is no place for them to give the flush signal. This commit fix this, refactor Queue.hasFlush: Boolean to Queue.flush: Option[Bool], makes user be able to pass the flush signal into Queue Module. * use zip to connect. * refactor docs. Co-authored-by: Megan Wachs <megan@sifive.com>
2021-11-03Add field grouping ScalaDoc for ArbiterIO (#2208)Abongwa Bonalais
* Update Arbiter.scala * Update src/main/scala/chisel3/util/Arbiter.scala changed group name Co-authored-by: Megan Wachs <megan@sifive.com> * minor changes on grouping ArbiterIO * removed unmatched closing brace * Remove groupdesc from Arbiter.scala * Added groupdesc to Aggregate.scala * Update Arbiter.scala * Update core/src/main/scala/chisel3/Aggregate.scala Co-authored-by: Megan Wachs <megan@sifive.com> * Update Arbiter.scala * Update src/main/scala/chisel3/util/Arbiter.scala Added suugestions. Co-authored-by: Megan Wachs <megan@sifive.com> * added suggestions from review * added suggestions from review * Resolved conflicts * update Arbiter.scala * Update core/src/main/scala/chisel3/Aggregate.scala deleted groudesc for ArbiterIO Co-authored-by: Megan Wachs <megan@sifive.com> * Update Scaladoc syntax * removed some lines * Better documentation * Removed @param and @gen * Update core/src/main/scala/chisel3/Aggregate.scala Co-authored-by: Megan Wachs <megan@sifive.com> * Update src/main/scala/chisel3/util/Arbiter.scala Co-authored-by: Megan Wachs <megan@sifive.com> * Added groupdesc to ArbiterIO * Update src/main/scala/chisel3/util/Arbiter.scala Co-authored-by: Megan Wachs <megan@sifive.com> * Update core/src/main/scala/chisel3/Aggregate.scala Co-authored-by: Megan Wachs <megan@sifive.com> * Update Arbiter.scala * Update src/main/scala/chisel3/util/Arbiter.scala Co-authored-by: Megan Wachs <megan@sifive.com> * Update Arbiter.scala Co-authored-by: Megan Wachs <megan@sifive.com>
2021-11-03Add field grouping ScalaDoc for other subclasses of Bundle (#2214)Abongwa Bonalais
* Add field grouping scaladocs for DecoupledIo * Added groupdesc to DecoupledIO * Added groupings for IrrevocableIO * Add groupings for ValidIO * Add field grouping scaladoc for PRNGIO * Add field grouping scaladoc for QueueIO * Added groupings for PipeIO * Update src/main/scala/chisel3/util/Decoupled.scala Commited Sugestion Co-authored-by: Megan Wachs <megan@sifive.com> * Update src/main/scala/chisel3/util/Decoupled.scala Co-authored-by: Megan Wachs <megan@sifive.com> * Update src/main/scala/chisel3/util/Decoupled.scala Co-authored-by: Megan Wachs <megan@sifive.com> * Update src/main/scala/chisel3/util/Decoupled.scala Co-authored-by: Megan Wachs <megan@sifive.com> * Update src/main/scala/chisel3/util/Decoupled.scala Co-authored-by: Megan Wachs <megan@sifive.com> * Update src/main/scala/chisel3/util/Valid.scala Co-authored-by: Megan Wachs <megan@sifive.com> * Update src/main/scala/chisel3/util/Valid.scala Co-authored-by: Megan Wachs <megan@sifive.com> * Update src/main/scala/chisel3/util/Valid.scala Co-authored-by: Megan Wachs <megan@sifive.com> Co-authored-by: Megan Wachs <megan@sifive.com>
2021-10-12Fix GaloisLFSR comments (#2178)Nic McDonald
2021-10-08Add nullary .fire to Valid and deprecate dummy version (#2156)Jack Koenig
Also replace all uses of .fire() with .fire
2021-10-05Deprecate auto-application of empty argument lists to parameterless ↵Jared Barocsi
functions (#2124) * Migrate nullary funcs to parameterless versions * Make deprecation message and dummy arguments clear and consistent Co-authored-by: Megan Wachs <megan@sifive.com>
2021-10-05Remove all Bundle cloneTypes and chiselRuntimeDeprecate its use (#2052)Megan Wachs
* Remove all manual cloneTypes and make it chisel runtime deprecated to add one * runtime deprecate cloneType with runtime reflection * [Backport this commit] Bundle: add check that override def cloneType still works (will be made an error later) * Plugin: make it an error to override cloneType and add a test for that * Docs: can't compile the cloneType anymore * BundleSpec: comment out failing test I cannot get to fail or ignore Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-09-06Fix #2112, handle `?->1` caseBoyang Han
2021-08-26add new APIs to BitPat (#2076)Jiuyang Liu
* add Y and N to BitPat. * add ## for BitPat. * add rawString API. * use rawString in decoder * add select and slice to BitPat.
2021-08-12Pass truth table to espresso using stdin instead of temp fileBoyang Han
2021-08-03Added flush capability to Queue (#2030)anniej-sifive
Co-authored-by: Megan Wachs <megan@sifive.com> Co-authored-by: Deborah Soung <debs@sifive.com>
2021-07-14Espresso Decoder (#1964)Jiuyang Liu
Co-authored-by: Haoran Yuan <sinofp@tuta.io> Co-authored-by: Boyang Han <yqszxx@gmail.com>
2021-06-16Add computational complexity analysisBoyang Han
2021-06-16Refactor to a more `scala` formBoyang Han
2021-06-16Merge minimized table before return as a TruthTableBoyang Han
2021-06-16implement QMC.Boyang Han
2021-06-16Apply Jack's Review Jiuyang Liu
1. `TruthTable` is final now. 2. add return type for `TruthTable` Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-06-16add documentation for DecodeTableAnnotation.Jiuyang Liu
2021-06-16remove all timeouts by review.Jiuyang Liu
2021-06-16async decoder with 5 seconds timeout.Jiuyang Liu
2021-06-16add a simple decoder API.Jiuyang Liu
2021-06-16implement abstract Minimizer as a general API.Jiuyang Liu
2021-06-16fix for 2.13Jiuyang Liu
2021-06-16TruthTable can merge same inputs now.Jiuyang Liu
2021-06-16implement DecodeTableAnnotation for decode table caching.Jiuyang Liu
2021-06-16implement TruthTable to represent a decode table.Jiuyang Liu
2021-06-10Stop Emitting BlackBoxResourceAnno (#1954)Schuyler Eldridge
* Change HasBlackBoxResource to Resolve Resources Change HasBlackBoxResource to resolve resources immediately and emit BlackBoxInlineAnno instead of a BlackBoxResourceAnno. This removes the need for a FIRRTL compiler to grok the Java Resource API in order to handle BlackBoxResourceAnno. Emit BlackBoxInlineAnno from HasExtModuleResource instead of BlackBoxResourceAnno. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-05-25throw exception if BitPat width is 0 (#1920)Jiuyang Liu
* spot a bug when BitPat width is 0 * fix #1919 Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-05-20Implement PLA (#1912)Jiuyang Liu
* implement pla * implement test for pla * implement inverter matrix of PLA generator * fix for review. Co-authored-by: Boyang Han <yqszxx@gmail.com>
2021-05-10implement equal to BitPat. (#1867)Jiuyang Liu
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-05-09Fix ShiftRegister with 0 delay. (#1903)Jiuyang Liu
* Add test to check ShiftRegister(s) with delay is 0. This should break ShiftRegister(x, 0) since last is not exist in a empty Seq. Originally, test only test 1 to 4, which missed a potential bug from #1723. * Fix ShiftRegister with 0 delay. if ShiftRegisters is empty, java will complain: ``` java.util.NoSuchElementException scala.collection.LinearSeqOptimized.last(LinearSeqOptimized.scala:150) ``` This fix this issue and return `in` directly when ShiftRegister size is 0. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-05-06add ShiftRegisters to expose register inside ShiftRegister. (#1723)Jiuyang Liu
* add ShiftRegisters to expose register inside ShiftRegister. * use Seq.iter for oneline implementation.
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