summaryrefslogtreecommitdiff
path: root/src/main/scala/chisel3/util
AgeCommit message (Expand)Author
2019-05-10Change LFSR16 deprecation from 3.3 -> 3.2Schuyler Eldridge
2019-05-10Fix LFSR regressionAndrew Waterman
2019-05-09PRNG state UInt->Vec[Bool], make async reset safeSchuyler Eldridge
2019-05-09Deprecate LFSR16, use FibonacciLFSR internallySchuyler Eldridge
2019-05-09Add chisel3.util.random lib w/ LFSR generatorSchuyler Eldridge
2019-03-21Remove @chiselName from MixedVec (#1045)Richard Lin
2019-03-18Split #974 into two PRs - scalastyle updates (#1037)Jim Lawson
2019-03-15Use TransitName for improved Pipe naming (#1024)Schuyler Eldridge
2019-03-14Decouple implementation details from LoadMemoryAnnotation. (#1034)Jim Lawson
2019-03-11ScalaDocs improvement for utils Math, MixedVec (#1019)Richard Lin
2019-02-25Docs for ListLookup (#1028)Richard Lin
2019-02-19Add HasBlackBoxPath to BlackBoxUtils.scala (#903)Albert Chen
2019-02-19ScalaDoc for Mux (examples added) (#1014)Martin Schoeberl
2019-02-19Add Scaladoc for chisel3.util.TransitNameSchuyler Eldridge
2019-02-19Util doc lsfr (#1021)Chick Markley
2019-02-19Documentation for Reg utilities (#1018)Martin Schoeberl
2019-02-19ScalaDoc for OneHot (#1016)Martin Schoeberl
2019-02-18Add requirement that Pipe latency >= 0Schuyler Eldridge
2019-02-18Add Scaladoc for chisel3.util.PipeSchuyler Eldridge
2019-02-18Add Scaldoc for chisel3.util.ValidSchuyler Eldridge
2019-01-25WireDefault instead of WireInit, keep WireInit around (#986)Martin Schoeberl
2019-01-22Changes to BoringUtils Scaladoc, paramater nameSchuyler Eldridge
2019-01-22Fix BoringUtils deduplication bugSchuyler Eldridge
2019-01-21Unify internal (chisel3.core) and external (chisel3 / chisel3.experimental) M...Richard Lin
2018-12-04Add asBool, deprecate toBoolJack Koenig
2018-12-04Add asBools, deprecate toBoolsJack Koenig
2018-11-02Fix Queue.io.count when entries=1 (#918)Andrew Waterman
2018-10-29Fix LoadMemoryTransform for Instance Annotations (#914)Schuyler Eldridge
2018-10-12Strong enums (#892)Hasan Genc
2018-10-03Modify ReadyValidIO noenq to set the data payload to DontCare. (#902)Steve Burns
2018-09-07Put do_* methods in SourceInfoTransformMacro groupSchuyler Eldridge
2018-08-31Support for verilog memory loading. (#840)Chick Markley
2018-08-23Add FlattenInstance APISchuyler Eldridge
2018-08-23Add InlineInstance APISchuyler Eldridge
2018-08-22Implement varargs MixedVec APIEdward Wang
2018-08-22Make MixedVec wire init consistent with VecInitEdward Wang
2018-08-22Remove dynamic indexing for nowEdward Wang
2018-08-22MixedVec: clarify dynamic indexing of heterogeneous elementsEdward Wang
2018-08-22Remove redundant := methodEdward Wang
2018-08-22MixedVec implementationEdward Wang
2018-08-07BoringUtils / Synthesizable Cross Module References (#718)Schuyler Eldridge
2018-07-31Cleanup implicit conversions (#868)Jack Koenig
2018-07-06Undeprecate log2Up and log2Down (#846)Jack Koenig
2018-07-04Prefer litValue, eliminate litToBigIntducky
2018-07-04Style fixesducky
2018-07-04work on new style literal accessorsducky
2018-06-25Correcting documentation errors in Arbiter.scala (#839)Brendan Sweeney
2018-06-18Fixed UIntToOH(x, 1) invocation with x.width == 0 (#778)Wesley W. Terpstra
2018-05-24Fix UIntToOH for output widths larger than 2^(input width) (#823)Andrew Waterman
2018-02-28Refactor Annotations (#767)Jack Koenig
generated by cgit v1.2.3 (git 2.25.1) at 2026-01-31 18:33:12 +0000