chiselX - Chisel with SFC compatibility

Age	Commit message (Collapse)	Author
2024-06-04	Culprit is the map in random/LFSR.scala. Delete it	Aditya Naik
	+ compiler rewrites
2022-01-10	Apply scalafmt	Jack Koenig
	Command: sbt scalafmtAll
2020-10-01	Move Chisel3 to SPDX license conventions (#1604)	Chick Markley
	Change source and other relevant files to use SPDX license LICENSE file moved from src/ to ./ Changed license file to refer to this per recommendation using_spdx_license_list_short_identifiers WARNING: Tests fail with as of yet undiagnosed error ``` [error] Failed: Total 691, Failed 19, Errors 0, Passed 672, Ignored 15 [error] Failed tests: [error] chiselTests.QueueSpec [error] examples.VendingMachineGeneratorSpec [error] chiselTests.HarnessSpec [error] chiselTests.ConnectSpec [error] chiselTests.aop.SelectSpec [error] chiselTests.PopCountSpec [error] chiselTests.CloneModuleSpec [error] (Test / test) sbt.TestsFailedException: Tests unsuccessful [error] Total time: 379 s (06:19), completed Sep 30, 2020 12:38:17 AM sbt:chisel3> ```
2019-05-09	PRNG state UInt->Vec[Bool], make async reset safe	Schuyler Eldridge
	Changes the internal state of PRNG to use Vec[Bool] instead of UInt. This fixes an @aswaterman identified future problem with asynchronous reset. A register with an asynchronous reset can only be reset to a literal. Previously, an LFSR would store state as a UInt. If it was not parameterized with a seed it should have its least significant bit reset to something to avoid locking up. It's ideal to not reset the full UInt (better test coverage, decreased reset fanout). However, it's difficult to only reset one bit of a UInt. Conversely, it's trivial to reset one bit of a Vec[Bool]. This also moves PRNG/LFSR closer to a canonical representation of their internal state, i.e., it's natural to think of generalizing Vec[Bool] to arbitrary finite fields (Vec[A <: Field]) whereas UInt is tightly coupled to GF2. Minor updates: - Updates/fixes to some scaladoc - Add assertion to period test to make sure LFSR is changing Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-09	Add chisel3.util.random lib w/ LFSR generator	Schuyler Eldridge
	Builds out PRNG and LFSR type hierarchy. PRNG is the base class of LFSR of which Galois and Fibonacci are concrete implementations. PRNGs contain state (a UInt) and an update (delta) function. They have a compile-time optional seed to set the PRNG state. The seed/state can also be set at run-time. PRNGs can be run-time parameterized based on how many updates they should do per cycle and whether or not to send the seed through step-count state updates before loading it. (h/t @jwright6323) LFSRs are parameterized in a reduction operation (XOR or XNOR). An LFSR that does NOT have a seed will be automatically initialized to a minimally safe state (set/reset one bit) based on their reduction operation. (h/t @aswaterman) Adds Galois and Fibonacci LFSRs that define appropriate update functions. Companion objects provide helpers to automatically generate maximal period variants. Taps are provide for a very large set of widths. The LFSR companion object provides an apply method to generate a Fibonacci LFSR random variable (like the old LFSR16).