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path: root/src/main/scala/chisel3/testers
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2018-12-04Add asBool, deprecate toBoolJack Koenig
2018-08-29Inhibit aggressive resource file name mangling. (#884)Jim Lawson
* Inhibit aggressive resource file name mangling. This addresses #883. * Use common method to write resources to a directory to keep file names consistent.
2018-08-07BoringUtils / Synthesizable Cross Module References (#718)Schuyler Eldridge
This adds an annotator that provides a linkage to the FIRRTL WiringTransform. This enables synthesizable cross module references between one source and multiple sinks without changing IO (the WiringTransform bores through the hierarchy). Per WiringTransform, this will connect sources to their closest sinks (as determined by BFS) or fail if ownership is indeterminate. Make TesterDriver.execute work like Driver.execute: - annotations are included when running FIRRTL - custom transforms are run automatically Also, add a bore method to BoringUtils that allows you to do one source to multi-sink mapping in a single call. This adds a test that this is doing the same thing as the equivalent call via disjoint addSink/addSource. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-07-04properly fix undefined clock/reset issuesducky
2018-01-02Support for inner classes, implicit parameter lists, supertypessducky64
2018-01-02Autoclonetype initial prototypeducky
2017-08-17Make Reset a trait (#672)Jack Koenig
Bool implements Reset. Compatibility package includes an implicit conversion from Reset to Bool.
2017-05-11Scope resources - move them down into chisel3 directory - fixes #549 (#610)Jim Lawson
2017-02-01Move backend compilation utilities (#400)Jim Lawson
* Move copyResourceToFile() to BackendCompilationUtilities. * Move BackendCompilationUtilities into a firrtl util package. Some of this could be moved into a more general tools package, but since chisel3 already has a dependency on firrtl ... * Push util down into firrtl so as not to conflict with scala.util. * Use new createTestDirectory. Fixes #452.
2017-01-27Deprecate firrtlToVerilog in favor of compileFirrtlToVerilog (#367)Jack Koenig
Resolves #357 Also remove uses of firrtlToVerilog within chisel3. Invoking Firrtl programmatically is preferred to on the command line. Update README to indicate that Firrtl need not be installed.
2017-01-27Provide package-level text to reduce ScalaDoc white space. (#432)Jim Lawson
2016-11-29Add feature warnings to build, fix feature warnings, fix some documentation ↵Richard Lin
(#387)
2016-10-14Implement a standardized execution scheme for chiselchick
Provide support for chisel options Provide support for firrtl options when called as part of chisel compile provide command line support the above options via scopt provide and execution result class that can be used when chisel3 is part of some externally controlled toolchain
2016-09-29Consolidate CompileOptions and re-enable NotStrict pending macro work.Jim Lawson
2016-09-29Massive rename of CompileOptions.Jim Lawson
Massage CompileOption names in an attempt to preserve default (Strict) CompileOptions in the absence of explicit imports. NOTE: Since the default is now strict, we may encounter errors when we generate connections for clients (i.e., in Vec.do_apply() when we wire up a sequence). We should really thread the CompileOptions through the macro system so the client's implicits are used.
2016-08-29Rename CompileOptions implicit objects.Jim Lawson
2016-08-29Pass compileOptions as an implicit Module parameter.Jim Lawson
2016-07-19Merge branch 'sdtwigg_rebase_renamechisel3' into sdtwigg_wrap_renamechisel3Jim Lawson
2016-07-18Update Chisel -> chisel3 references.Jim Lawson
2016-07-18Rename "Chisel" to "chisel3" (only git mv).Jim Lawson