| Age | Commit message (Collapse) | Author |
|---|
|
withClockAndReset, withReset, and withClock allow changing the implicit clock and reset.
Module.clock and Module.reset provide access to the current implicit clock and reset.
|
|
Used for stitching Verilog inout through Chisel Modules (from BlackBox
to BlackBox)
|
|
|
|
Retain un-deprecated SeqMem in compatibility mode, deprecate in chisel3.
|
|
|
|
* Name propagation
* chiselName everywhere at best-effort level
* Better collision handling
* Allow recursing into inner anonymous functions
* Add for loop and anonymous inner function tests
|
|
Record gives uses the power to create collections of heterogenous elements.
Bundle is a special case of Record that uses reflection to populate the
elements of the collection. Bundle also attempts to implement cloneType whereas
users of Record are required to supply one.
|
|
* Mark Annotation and FixedPoint as experimental
Fix tests and other references to these constructs
* Made experimental imports more specific where possible
|
|
|
|
* Support for creating chisel annotations that are consumed by firrtl
Update annotation serialization in Driver
Add DiamondAnnotation Spec that illustrates how to do simple annotations
frontEnd must have dependency on firrtl
Add annotation method to Module
Circuit has extra optional parameter that is Seq of Annotations
In Builder add annotation buffer to DynamicContext to store annotations created in modules
Added explicit types on naming api methods to avoid type confusion
Because some names are not available until elaboration create intermediate ChiselAnnotation that
gets turned into a firrtl Annotation after elaboration
In execute pass firrtl text and annotation to firrtl are now passed in through optionManager, though
intermediate file .fir and .anno files are still created for inspection and/or later use
* Somehow missed ChiselAnnotation
* fixes for Jack's review of PR
|
|
(#387)
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
compatibility package object
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Also restrict black boxes to not allow hardware inside of them since it was
being silently dropped anyway.
Resolves #289
|
|
* FixedPoint number support for chisel3
FixedPoint numbers have a width and a binary position
Either, neither or both maybe inferred.
Firrtl will convert these to SInts during lowering passes
* Fixes based on Jack's comments on PR #328
* Add experimental warning to FixedPoint class and object
* Fixed comment per Adam's comment on PR #328
|
|
|
|
This reverts commit 10f170110cd00e7e5e0b428c0490594dac4db225.
|
|
This reverts commit 3ea7faaad0c3e349c531fabc8a75440337bdc235, reversing
changes made to 7aea39d4deac62d5477904f4bf4381c3482c41d0.
Update chisel-testers before commiting this change (deleting EnqIO/DeqIO).
|
|
|
|
|
|
|
|
|
|
Printable is a new type that changes how printing of Chisel types is represented
It uses an ordered collection rather than a format string and specifiers
Features:
- Custom String Interpolator for Scala-like printf
- String-like manipulation of "hardware strings" for custom pretty-printing
- Default pretty-printing for Chisel data types
|
|
|
|
|
|
Revive support for firrtl flip direction.
Remove compileOptions.internalConnectionToInputOk
|
|
|
|
|
|
|
|
Remove .Lit(x) usage.
Undo "private" scope change.
Change "firing" back to "fire".
Add package level NODIR definition.
|
|
|
|
|
|
|
|
Need to convert UInt(x) into UInt.Lit(x) or UInt.width(x)
|
|
Compiles but fails tests.
|
|
|
|
|
