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path: root/src/main/scala/chisel3/Driver.scala
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2019-01-07Fix build error due to scala bug #11125 (#967)Nick Hynes
JDK 11 `java.lang.String#lines` conflicts with Scala `StringOps#lines`. This has been fixed in scalac 2.12.8 but projects using 2.11 in their cross-build need the `Predef.augmentString` patch. [Scala bug & fix reference](https://github.com/scala/bug/issues/11125)
2018-11-26Trim Stack Trace (#931)Albert Chen
- Trim stack trace to show better, reduced information to the user - Add --full-stacktrace to FIRRTL option to show full stack trace
2018-09-28Add dumpAnnotations method to DriverSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-09-20Documentation tweaksedwardcwang
2018-07-02Direct to FIRRTL (#829)Jack Koenig
Provide direct conversion from ChiselIR to FIRRTL. Provide Driver support for dumping ProtoBuf.
2018-02-28Refactor Annotations (#767)Jack Koenig
* Generalize ChiselAnnotation This allows us to delay creation of Annotations till elaboration is complete. Also update all annotation-related code. * Add RunFirrtlTransform Use a Chisel-specific RunFirrtlTransform API to preserve behavior of old ChiselAnnotation (now called ChiselLegacyAnnotation) * Use unique test directories in ChiselRunners.compile
2017-11-21Correct documentation example for chisel3.Driver (#719)Schuyler Eldridge
This corrects the documented example for chisel3.Driver to mixin traits and not the related case classes. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2017-09-06Added API to get Verilog from Chisel (#676)Adam Izraelevitz
* Added API to get Verilog from Chisel * Removed second emitVerilog implementation, added scaladoc
2017-05-31Dont try to instantiate firrtl.Transform from AnnotationJack Koenig
Also make transform instantiation deterministic
2017-04-13Module Hierarchy Refactor (#469)Richard Lin
2017-02-01Move backend compilation utilities (#400)Jim Lawson
* Move copyResourceToFile() to BackendCompilationUtilities. * Move BackendCompilationUtilities into a firrtl util package. Some of this could be moved into a more general tools package, but since chisel3 already has a dependency on firrtl ... * Push util down into firrtl so as not to conflict with scala.util. * Use new createTestDirectory. Fixes #452.
2017-01-31Fix spelling of ChiselExecutionSuccessJack
2017-01-31Move blackbox verilog implementations within reach of verilator (#453)Chick Markley
* Move blackbox verilog implementations within reach of verilator Blackbox implementers can annotate the modules with information on where to get the source verilog This API is very lightweight, real work is done in firrtl in companion PR Added some verilog to BlackBoxTest.v resource for testing * if a file named black_box_verilog_files.f exists add a -f black_box_verilog_files.f to the verilog to cpp command
2017-01-27Deprecate firrtlToVerilog in favor of compileFirrtlToVerilog (#367)Jack Koenig
Resolves #357 Also remove uses of firrtlToVerilog within chisel3. Invoking Firrtl programmatically is preferred to on the command line. Update README to indicate that Firrtl need not be installed.
2017-01-26doesn't lose old firrtl options annotations + transforms (#458)Angie Wang
Fixing a bug in passing down execution options to firrtl
2017-01-10Make stop() immediately end simulation for Verilator tests (#434)Jack Koenig
2016-12-14Final steps for annotations getting from chisel to firrtl (#405)Chick Markley
Pass transforms along with Annotations when calling firrtl compiler This introduces new requirement that firrtl.Transform subclasses (that are associated with an annotation) do not have parameters in their default constructor Add new test for NoDedup annotation that shows how to annotate a module instance
2016-12-07Support for creating chisel annotations that are consumed by firrtl (#393)Chick Markley
* Support for creating chisel annotations that are consumed by firrtl Update annotation serialization in Driver Add DiamondAnnotation Spec that illustrates how to do simple annotations frontEnd must have dependency on firrtl Add annotation method to Module Circuit has extra optional parameter that is Seq of Annotations In Builder add annotation buffer to DynamicContext to store annotations created in modules Added explicit types on naming api methods to avoid type confusion Because some names are not available until elaboration create intermediate ChiselAnnotation that gets turned into a firrtl Annotation after elaboration In execute pass firrtl text and annotation to firrtl are now passed in through optionManager, though intermediate file .fir and .anno files are still created for inspection and/or later use * Somehow missed ChiselAnnotation * fixes for Jack's review of PR
2016-11-18Change Verilator invocation to use O1jackkoenig
Workaround for: http://www.veripool.org/issues/1101-Verilator-Fix-SmallName-for-ParamTypeDType
2016-11-17Eliminate some doc warningsducky
2016-10-19Change verilogToCpp to use O0jackkoenig
This causes Verilator tests to compile faster and use less memory
2016-10-14Implement a standardized execution scheme for chiselchick
Provide support for chisel options Provide support for firrtl options when called as part of chisel compile provide command line support the above options via scopt provide and execution result class that can be used when chisel3 is part of some externally controlled toolchain
2016-10-06Remove non-standard sbt-buildinfo settings; write buildinfo to firrtl file.Jim Lawson
2016-10-06Merge branch 'master' into buildinfoJim Lawson
2016-10-06Update Driver: Check the simulation exit code #281Jim Lawson
Merge with master and support checking for failure with an explicit assertion message.
2016-10-05Print Chisel version when Driver object is created.Jim Lawson
2016-10-05Add sbt-buildinfo support.Jim Lawson
2016-09-01Move connection implicits from Module constructor to connection methods.Jim Lawson
Eliminate builder compileOptions.
2016-08-30Merge branch 'master' into gsdtJim Lawson
2016-08-30Allow compileOptions as optional arguments to elaborate() and emit().Jim Lawson
2016-08-30Correct parameter name (topModule) in ScalaDoc.Jim Lawson
2016-08-21provides signal name methods for firrtl annotation and chisel testersDonggyu Kim
* signalName: returns the chirrtl name of the signal * pathName: returns the full path name of the signal from the top module * parentPathName: returns the full path of the signal's parent module instance from the top module * parentModName: returns the signal's parent **module(not instance)** name.
2016-06-28Merge branch 'master' into renamechisel3Jim Lawson
2016-06-20Rename "package", "import", and explicit references to "chisel3".Jim Lawson
2016-06-20Rename chisel3 package.Jim Lawson
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