| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2015-09-18 | Improve IR class hierarchy | Andrew Waterman | |
| - Rename Alias to Node to match FIRRTL notion - Remove poorly-named Immediate and replace root of hierarchy with Arg | |||
| 2015-08-31 | Fix val io = new Bundle{...}.flip | Andrew Waterman | |
| Now, we emit all I/Os inside a bundle named io. | |||
| 2015-08-28 | Use FIRRTL smem for SeqMem | Andrew Waterman | |
| Read enables and read-write ports aren't working yet. | |||
| 2015-08-28 | Add poison node | Andrew Waterman | |
| 2015-08-27 | Fix bug where flipping top-level I/O had no effect | Andrew Waterman | |
| The fix is to propagate the flip to the fields in the bundle. | |||
| 2015-08-26 | Remove Mem from Data hierarchy | Andrew Waterman | |
| Just like Reg, state elements are not Data. | |||
| 2015-08-20 | Remove Port/Kind IR nodes, which merely wrap Data | Andrew Waterman | |
| 2015-08-17 | Delete unused IR nodes | Andrew Waterman | |
| 2015-08-13 | clean up Id and Builder.globalRefMap | Henry Cook | |
| 2015-08-13 | Streamline files, breaking up Core.scala and resorting some smaller ones | Henry Cook | |
 |
index : chiselX | |
| Chisel with SFC compatibility |
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