chiselX - Chisel with SFC compatibility

Age	Commit message (Collapse)	Author
2021-03-18	Don't toggle top.cpp clock and reset on same cycle (#1820)	Schuyler Eldridge
	Change top.cpp to deassert reset one time unit before the clock asserts. This avoids a Verilator simultation issue in top.cpp where the eval() function is only called once per simultation loop. If the clock and reset are both changed and eval() is only called once, then any combinational update due to a change in reset is not visible to the sequential logic. This avoids issues where the downstream compilation utilities move synchronous reset logic outside of an always block that describes a synchronous reset flip flop. Reset now deasserts on time unit 10 and the clock ticks on time unit 11. h/t @albert-magyar Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2020-03-02	Cleanup aspects (#1359)	Adam Izraelevitz
	* Clean up aspects * Refactored InjectingAspect with InjectorAspect * Made AspectLibrary work with objects * Cleaned up code * Apply suggestions from code review * Added tests, removed deprecated newInstance call * Backed out removal of newInstance as exceptions were different * Removed trailing commas
2017-05-11	Scope resources - move them down into chisel3 directory - fixes #549 (#610)	Jim Lawson

2017-01-10	Make stop() immediately end simulation for Verilator tests (#434)	Jack Koenig

2016-09-21	Make implicit clock name consistent (#288)	Andrew Waterman
	In the Chisel frontend, the implicit clock is named clock, but in the generated FIRRTL, it is named clk. There is no reason for this discrepancy, and yet fixing it is painful, as it will break test harnesses. Better to take the pain now than later. Resolves #258.
2016-05-09	remove vpi source files	Donggyu Kim

2016-01-23	Change implicit clock name to clk to match Chisel2	Andrew Waterman
	This allows us to share Verilog test harnesses between the two.
2015-12-11	Refactor tests to use stop() and assert() instead of io.error/io.done	ducky
	Gate assert, printf, stop by reset Fix testbenches that never worked Change simulation prints to display cycle at which test was signaled to end, not when simulator stops Better documentation for Counter
2015-11-06	return -1 on simulation timeout	Henry Cook

2015-11-04	Remove Parameters library and refactor Driver.	Henry Cook
	In addition to removing all the extraneous Driver invocations that created various top-level Parameters instances, this commit also lays the groundwork for stanza-firrtl/verilator based testing of Modules that extend BasicTester. The execution-based tests have been updated accordingly. They will only succeed if firrtl and verilator binaries have been installed. Further work is needed on individual tests to use assertions instead of .io.error.
2015-09-23	Remove unused files	ducky

2015-08-08	verilog emulator resources	Henry Cook

2015-04-27	add headers	jackbackrack