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2022-01-19util: add GrayCode (#2353) (#2354)mergify[bot]
(cherry picked from commit 91d7baa8e7162d736f46b6d4964b09016d2dd172) Co-authored-by: Kevin Laeufer <laeufer@cs.berkeley.edu>
2021-12-15Refactor TruthTable to use Seq (#2217)Jiuyang Liu
This makes the resulting Verilog from decoding a TruthTable deterministic.
2021-08-30SyncReadMem: fix bug with read(addr) and add some formal tests (#2092)Kevin Laeufer
2021-08-25replace custom model checker with chiseltest formal verify command (#2075)Kevin Laeufer
* replace custom model checker with chiseltest formal verify command * integration-tests can make use of chiseltest This is a compromise solution to avoid issues with binary compatibility breaking changes in chisel3. * ci: move integration tests into separate job * run integration tests only for one scala version * ci: install espresso for integration tests * Update build.sbt Co-authored-by: Jack Koenig <jack.koenig3@gmail.com> Co-authored-by: Jack Koenig <jack.koenig3@gmail.com>