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2022-10-23Fix for <> to BlackBox.IO with Compatibility Bundles (#2801) (#2803)mergify[bot]
MonoConnect.traceFlow now properly handles coerced directions. Also minor improvement to getClassName especially useful in test case printf debugging. (cherry picked from commit 3aba755bdcf996c0fbd846d13268fd6641b29e96) Co-authored-by: Megan Wachs <megan@sifive.com>
2022-10-23Don't invalidate ExtModule ports in an explicitInvalidate = true context ↵mergify[bot]
(backport #2795) (#2799) * Don't invalidate ExtModule ports in an explicitInvalidate = true context (#2795) * Don't invalidate ExtModule ports in an explicitInvalidate = true context ExtModule ports were previously invalidated in the emitted FIRRTL, which is correct in a NonStrict / `Chisel._` compatibility context but not in newer chisel3 code where `explicitInvalidate = true`. (cherry picked from commit 8e24a281545d25f6501dcc872eabdfb30bacd69d) # Conflicts: # core/src/main/scala/chisel3/BlackBox.scala * Resolve backport conflicts Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-10-19Don't modify the Builder prefix if reinvoking suggestName on a Data ↵mergify[bot]
(backport #2789) (#2790) * Only set the chisel3 Builder prefix during the first invocation of suggestName (cherry picked from commit b684506abab2f7b99d56181d548cb8119d317323) # Conflicts: # core/src/main/scala/chisel3/internal/Builder.scala * Add simple test to show bug fix (cherry picked from commit 255068b105de77a045a0016e3a157b52a81c86d6) * Fix merge conflict * Fix test to not use Hardware inside a bundle for prefixing Co-authored-by: Jared Barocsi <jared.barocsi@sifive.com>
2022-10-18Add traceNameV2 for backwards compat. of traceName (#2784) (#2786)mergify[bot]
Add utilities to enable backwards compatibility of the Trace.traceName API to Chisel 3.5.x. This adds a Trace.traceNameV2 utility which aliases to Trace.traceName. This also removes the TraceNameAnnotation and renames it TraceAnnotation. In 3.5.x, traceName will point at TraceNameAnnotation (which has don't touch behavior) and will be deprecated telling people to use traceNameV2 which will point at TraceAnnotation (which does not have don't touch behavior). This will require fixups to the backport associated with this PR. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> (cherry picked from commit 47b7227e1ac7ccb0d48cefef03510542cc7e157e) # Conflicts: # core/src/main/scala/chisel3/experimental/Trace.scala Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2022-10-17Add opt-in AutoCloneType for Records (backport #2781) (#2785)mergify[bot]
* Add opt-in AutoCloneType for Records (#2781) There is a new trait, chisel3.experimental.AutoCloneType that is mixed in to Bundle and can optionally be mixed in to user-defined Records. The compiler plugin prints a deprecation warning on any user-defined implementation of cloneType, telling the user to mix in AutoCloneType before upgrading to 3.6. (cherry picked from commit a234fd48ac8f5942c38fef5797292014e407b586) # Conflicts: # core/src/main/scala/chisel3/Aggregate.scala # plugin/src/main/scala/chisel3/internal/plugin/BundleComponent.scala * Resolve backport conflicts * Do not make MixedVec extend AutoCloneType It is a binary incompatible change that can wait for 3.6. * Waive MiMa false positives Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-10-10Fix traceName module type to RawModule (backport #2765) (#2768)mergify[bot]
* Fix traceName module type to RawModule (#2765) Change the type of modules that the traceName API can be used for from "Module" to "RawModule". This fixes a bug where this API couldn't be used for RawModules even though it totally works. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> (cherry picked from commit 74f1c85060cc72ebffe59a49f8d4539a464a4a19) * Fix binary compatibility issue Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-10-07Make nested IsInstantiables with Data in them work (#2761) (#2766)mergify[bot]
* Add unit test for Issue 2760 * checkpoint: Fix for nested instance * remove comments about stuff not working * make the test check the output a little more * relax the requirement on returning empty ioMap * Update core/src/main/scala/chisel3/experimental/hierarchy/core/Lookupable.scala * Update core/src/main/scala/chisel3/Data.scala * Update core/src/main/scala/chisel3/experimental/hierarchy/core/Lookupable.scala Co-authored-by: Jack Koenig <koenig@sifive.com> * Update src/test/scala/chiselTests/experimental/hierarchy/InstanceSpec.scala Co-authored-by: Jack Koenig <koenig@sifive.com> * Update core/src/main/scala/chisel3/experimental/hierarchy/core/Lookupable.scala * Add another unit test which unfortunately still passes * Update core/src/main/scala/chisel3/Data.scala * Update src/test/scala/chiselTests/experimental/hierarchy/InstanceSpec.scala Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit 1f9f26dc2bffcb4cc4daf2dc16c5cb455c6769ef) Co-authored-by: Megan Wachs <megan@sifive.com>
2022-10-06Update toPrintable for Enums (#2707) (#2763)mergify[bot]
(cherry picked from commit 0ff99ca8d573e3487ef496a21c95d962689c3cba) Co-authored-by: Aditya Naik <91489422+adkian-sifive@users.noreply.github.com>
2022-09-29Add lexical scope checks to Assert, Assume and Printf (#2706) (#2753)mergify[bot]
(cherry picked from commit f462c9f9307bebf3012da52432c3729cd752321c) Co-authored-by: Aditya Naik <91489422+adkian-sifive@users.noreply.github.com>
2022-09-15Change description for SInt unary negation (#2729) (#2734)mergify[bot]
Referenced to: chipsalliance/chisel3#2728 (cherry picked from commit a4dae9c340c71c063cf0fdec290a6e011b82746d) Co-authored-by: Marco Origlia <30799310+moriglia@users.noreply.github.com>
2022-09-01Remove incorrect clock warning on Mem.read (backport #2721) (#2722)mergify[bot]
* Remove incorrect clock warning on Mem.read (#2721) Mem.read is combinational and thus unaffected by the clock, and so it does not make sense to issue warnings about the current clock in this context. (cherry picked from commit 5fdf74f95e64cb69d6097547f20d789a83dbd735) * Keep old version of MemBase.clockWarning for binary compatibility This method is impossible for users to call, but it is easy enough to keep around a version of it to make MiMa happy. Co-authored-by: Andrew Waterman <andrew@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-09-01Revert "Privatize trait VerifPrintMacros (#2683)" (#2718) (#2719)mergify[bot]
This reverts commit de76e70bc5905fc4ebc8a2e323e16620fa6832ec. (cherry picked from commit e1e0503d969c8f4bb68a3beedebca5d9238192fd) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-08-31Wires should have source location information in firrtl (#2714) (#2716)mergify[bot]
- Remove line defeating having wire locators `implicit val noSourceInfo = UnlocatableSourceInfo` from `WireDefault#apply` - Add test to show locators (cherry picked from commit f701a9f8151891e3bf9019cd3229cb3f2cd1833b) Co-authored-by: Chick Markley <chick.markley@sifive.com>
2022-08-29Fix OpaqueSlot handling of contextual names (#2708) (#2712)mergify[bot]
We need to ensure that contextual names stay contextual (ie. sensitive to the module context which is important for naming ports). (cherry picked from commit cee255216c4a1bb658a2d8ddc03d966ce7ffb877) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-08-25Bugfix - OpaqueSlot replace invalid localName (backport #2701) (#2702)mergify[bot]
* Bugfix - OpaqueSlot replace invalid localName (#2701) (cherry picked from commit fb8ea2a2fac227f2570da992d7877de2eb1cf801) * Fix cloneTypes (#2703) Co-authored-by: Aditya Naik <91489422+adkian-sifive@users.noreply.github.com>
2022-08-24Backport .toTarget deprecation warning information (3.5.x) (#2697)Zachary Yedidia
2022-08-18Add generic `Data` equality (===) via extension method (#2669) (#2691)mergify[bot]
(cherry picked from commit 67cff8253740f19642006dba7eff58b1e5fa1291) Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
2022-08-16Add OpaqueType support to Records (backport #2662) (#2679)mergify[bot]
* Add OpaqueType support to Records (#2662) OpaqueTypes are essentially type aliases that hide the underlying type. They are implemented in Chisel as Records of a single, unnamed element where the wrapping Record does not exist in the emitted FIRRTL. Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit df5afee2d41b5bcd82d4013b977965c0dfe046fd) * Fix test compilation * Fix OpaqueType tests in RecordSpec Need to implement cloneType correctly and to warn instead of error when accessing .toTarget of non-hardware types because that is a warning (not error) in 3.5. * Waive MiMa false positives Co-authored-by: Aditya Naik <91489422+adkian-sifive@users.noreply.github.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-08-16Add a cookbook and publicly visible scaladoc for prefix, noPrefix (#2687) ↵mergify[bot]
(#2690) * Add a cookbook and publicly visible scaladoc for prefix, noPrefix (cherry picked from commit ae7dc30b3b99f1fbd91c35f54bc19be7c55f74a3) Co-authored-by: Megan Wachs <megan@sifive.com>
2022-08-16Privatize trait VerifPrintMacros (#2683) (#2685)mergify[bot]
(cherry picked from commit de76e70bc5905fc4ebc8a2e323e16620fa6832ec) Co-authored-by: Aditya Naik <91489422+adkian-sifive@users.noreply.github.com>
2022-08-15Printables for verification preconditions (backport #2663) (#2680)mergify[bot]
* Printables for verification preconditions (#2663) Add support for printable within assert and assume verification statements Co-authored-by: Girish Pai <girish.pai@sifive.com> Co-authored-by: Megan Wachs <megan@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit 7df5653309b5e48e1732b335610d9a7e8449f903) * Waive MiMa false positive Co-authored-by: Aditya Naik <91489422+adkian-sifive@users.noreply.github.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-08-13Add option to treat warnings as errors (backport #2676) (#2677)mergify[bot]
* Add option to treat warnings as errors (#2676) Add --warnings-as-errors option (cherry picked from commit 498946663726955c380a1e420f5d7b9630000aad) # Conflicts: # core/src/main/scala/chisel3/experimental/hierarchy/Definition.scala # core/src/main/scala/chisel3/internal/Builder.scala # src/main/scala/chisel3/aop/injecting/InjectingAspect.scala # src/main/scala/chisel3/stage/ChiselOptions.scala # src/main/scala/chisel3/stage/package.scala # src/main/scala/chisel3/stage/phases/Elaborate.scala * Resolve backport conflicts Co-authored-by: Zachary Yedidia <zyedidia@gmail.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-08-12Show equivalent warnings/errors only once (#2673) (#2675)mergify[bot]
(cherry picked from commit ae76ff4cb303a6646e48dc044be47051b67e7cbb) Co-authored-by: Zachary Yedidia <zyedidia@gmail.com>
2022-08-12Add ability to suppress enum cast warnings (#2671) (#2674)mergify[bot]
(cherry picked from commit 1ad820f7f549eddcd7188b737f59a240e48a7f0a) Co-authored-by: Zachary Yedidia <zyedidia@gmail.com>
2022-08-05Replace some options with nullable vars (backport #2658) (#2659)mergify[bot]
* Replace some options with nullable vars (#2658) Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit ac460bfeb16c8e7d0dc00975bb03f73c0fea2103) # Conflicts: # core/src/main/scala/chisel3/internal/Builder.scala * Fix backport conflicts (#2661) Co-authored-by: Zachary Yedidia <zyedidia@gmail.com>
2022-07-22ChiselEnum: make factory package private (#2639) (#2640)mergify[bot]
This is required in order to support peeks in chiseltest. (cherry picked from commit 26cd15a9943ca20829630d2feedac08a069291c2) Co-authored-by: Kevin Laeufer <laeufer@cs.berkeley.edu>
2022-07-21Deprecate chiselName and NoChiselNamePrefix trait (#2627) (#2633)mergify[bot]
Also remove all non-testing uses of chiselName. (cherry picked from commit 1c5d1b5317a0c9fe7ef9d15138065a817380a1e4) Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
2022-07-143.5x: Make explicit copy constructors for ExplicitCompileOptions (#2629)Megan Wachs
* Add copy constructors for compile options * Add tests for the copy constructors Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
2022-07-13New enhanced API for specifying Chisel to Firrtl Annotations (#2628) (#2631)mergify[bot]
(cherry picked from commit 4b10cf7a276e90b280c1fd57070566acac3d80d3) Co-authored-by: Girish Pai <girish.pai@sifive.com>
2022-07-08CompileOptions: add and use emitStrictConnects (#2622) (#2623)mergify[bot]
(cherry picked from commit 11e8cc60d6268301cff352b8a1d7c4d672b5be11) Co-authored-by: Megan Wachs <megan@sifive.com>
2022-07-06Implement trait for Chisel compiler to name arbitrary non-Data types (#2610) ↵mergify[bot]
(#2617) Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: Megan Wachs <megan@sifive.com> (cherry picked from commit 3ab34cddd8b87c22d5fc31020f10ddb2f1990d51) Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
2022-06-23Add DataMirror isIO, isReg, isWire (#2601) (#2602)mergify[bot]
(cherry picked from commit 7fa0d8bf1cafcdf141046476a100abf021bdcac4) Co-authored-by: Zachary Yedidia <zyedidia@gmail.com>
2022-06-22Pass optional name in ImportDefinitionAnno (#2592) (#2594)mergify[bot]
Used for separate elaboration of Definition and Instance (cherry picked from commit 48d57cc8db6f38fdf0e23b7dce36caa404c871b8) Co-authored-by: Girish Pai <girish.pai@sifive.com>
2022-06-16Define leading '_' as API for creating temporaries (backport #2580) (#2581)mergify[bot]
* Define leading '_' as API for creating temporaries Chisel and FIRRTL have long used signals with names beginning with an underscore as an API to specify that the name does not really matter. Tools like Verilator follow a similar convention and exclude signals with underscore names from waveform dumps by default. With the introduction of compiler-plugin prefixing in Chisel 3.4, the convention remained but was hard for users to use unless the unnnamed signal existed outside of any prefix domain. Notably, unnamed signals are most useful when creating wires inside of utility methods which almost always results in the signal ending up with a prefix. With this commit, Chisel explicitly recognizes signals whos val names start with an underscore and preserve that underscore regardless of any prefixing. Chisel will also ignore such underscores when generating prefixes based on the temporary signal, preventing accidental double underscores in the names of signals that are prefixed by the temporary. (cherry picked from commit bd94366290886f3489d58f88b9768c7c11fa2cb6) * Remove unused defaultPrefix argument from _computeName (cherry picked from commit ec178aa20a830df2c8c756b9e569709a59073554) # Conflicts: # core/src/main/scala/chisel3/Module.scala # core/src/main/scala/chisel3/experimental/hierarchy/ModuleClone.scala * Resolve backport conflicts * Waive false positive binary compatibility errors Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-06-13Add ImplicitInvalidate, to help migrate the explicitInvalidate compiler ↵mergify[bot]
option (#2575) (#2579) * Added ImplicitInvalidate trait with tests (cherry picked from commit 1356ced1b89ca35ae0cb1d1ab45227ec1776d5e7) Co-authored-by: Adam Izraelevitz <adam.izraelevitz@sifive.com>
2022-06-08Added migration for inferModuleReset (#2571) (#2573)mergify[bot]
Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit 3c6c044b6bdee850ad9ba375324abaf3813c557d) Co-authored-by: Adam Izraelevitz <adam.izraelevitz@sifive.com>
2022-06-07Add single argument Bits.extract (#2566) (#2568)mergify[bot]
(cherry picked from commit 255c56c3955a8c16191a6751e7d547cfcfd96705) Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
2022-06-06Add --warn:reflective-naming (backport #2561) (#2565)mergify[bot]
* Factor buildName into reusable function The new function is chisel3.internal.buildName. (cherry picked from commit 370ca8ac68f6d888dd99e1b9e63f0371add398cf) * Add --warn:reflective-naming This new argument (and associated annotation) will turn on a warning whenever reflective naming changes the name of a signal. This is provided to help migrate from Chisel 3.5 to 3.6 since reflective naming is removed in Chisel 3.6. (cherry picked from commit 97afd9b9a1155fa7cd5cedf19f9e0c15fbe899ec) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-06-03Deprecate implicit .U() and .S() syntax for literal bit extracts (backport ↵mergify[bot]
#2534) (#2559) * Deprecate .U() and .S() syntax for literal bit extracts (#2534) (cherry picked from commit cadaf33a650ef898fdab2f81244e4ad6a07a9ea8) # Conflicts: # macros/src/main/scala/chisel3/internal/sourceinfo/SourceInfoTransform.scala * Fix backport conflict (#2560) Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
2022-06-01Add formatted Printable interpolator `cf` (#2528) (#2553)mergify[bot]
This is a formatted version of the p"..." interpolator analogous to Scala's f"..." interpolator. The primary difference is that it supports formatting interpolated variables by following the variable with "%<specifier>". For example: printf(cf"myWire = $myWire%x\n") This will format the hardware value "myWire" as a hexidecimal value in the emitted Verilog. Note that literal "%" must be escaped as "%%". Scala types and format specifiers are supported and are handled in the same manner as in standard Scala f"..." interpolators. (cherry picked from commit 037f7b2ff3a46184d1b82e1b590a7572bfa6a76b) Co-authored-by: Girish Pai <girish.pai@sifive.com>
2022-05-29Deprecate accessing the name of non-hardware Data (#2550) (#2552)mergify[bot]
This includes (and is tested) for both the old .*Name APIs and .toTarget (cherry picked from commit 6e0d8d6b12e9d8f94c2cc43b92b2366ec70dfd50) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-05-27Make ExtModule port naming consistent with Module (#2548) (#2549)mergify[bot]
ExtModule now uses the same namePorts implementation as regular Modules. Previously, ExtModules only allowed port naming via runtime reflection. This meant that .suggestName and other naming APIs do not work. It also breaks FlatIO for ExtModule which is a potential replacement API for BlackBox's special `val io` handling. (cherry picked from commit 83cccfb782d9141bf2c843246c2a525c62392924) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-05-24Support Vecs of empty Bundles (#2543) (#2545)mergify[bot]
(cherry picked from commit a1e3a6b5324997864168111bee8c02a60abb0acc) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-05-19Support := views to DontCare (#2536) (#2539)mergify[bot]
(cherry picked from commit 77a6c93592d5766d66f199720fc6d69478005091) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-05-12Support separately elaborating definition and instance in ChiselStage ↵mergify[bot]
(backport #2512) (#2520) * Support separately elaborating definition and instance in ChiselStage (#2512) (cherry picked from commit a0aa4d1550e3fbde199a98529cffeb176fb4bed8) # Conflicts: # core/src/main/scala/chisel3/experimental/hierarchy/Definition.scala # core/src/main/scala/chisel3/experimental/hierarchy/Instance.scala # core/src/main/scala/chisel3/internal/Builder.scala * fixing imports (#2522) Co-authored-by: Deborah Soung <debs@sifive.com>
2022-04-25Fix error message for BlackBox without val io <: Record (#2504) (#2505)mergify[bot]
(cherry picked from commit f9aee1f72744abc6ee13aafc4d1a51a2783cbab8) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-04-20Generate a balanced tree with reduceTree (#2318) (#2499)mergify[bot]
The difference in logic depth for various paths now has a maximum of 1. Also make treeReduce order the same for 2.12 and 2.13 .grouped(_) returns an Iterator .toSeq on an Iterator returns a Stream in 2.12 and a List in 2.13 This can lead to changes in order when bumping from 2.12 to 2.13 that can be avoided by simply using an eager collection explicitly. Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit 6975f77f3325dec46c613552eac663c29011a67c) Co-authored-by: Martin Schoeberl <martin@jopdesign.com>
2022-04-19Allow creating memories without an implicit clock (#2494) (#2495)mergify[bot]
Fixes #2470 (cherry picked from commit 44165a259bb16733a41798edca6b554b13f1d54a) Co-authored-by: Kevin Laeufer <laeufer@cs.berkeley.edu>
2022-04-19verification: switch order of assert/assume and printf (#2484) (#2493)mergify[bot]
This is a quick fix for issue #2408 (cherry picked from commit d4ef9a96c4131252a0a49002a28be3391eb67258) Co-authored-by: Kevin Laeufer <laeufer@cs.berkeley.edu>
2022-04-18Fix small typos in doc comment (#2490) (#2492)mergify[bot]
(cherry picked from commit 52165fe2796d08c664069c148868aedc64ea3777) Co-authored-by: Lucheng Zhang <79909456+geekLucian@users.noreply.github.com>
generated by cgit v1.2.3 (git 2.25.1) at 2026-01-31 12:34:49 +0000