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This introduces a new experimental API for module instantiation that disentagles
elaborating the definition (or implementation) from instantiation of
a given module. This solves Chisel's longstanding reliance on
"Deduplication" for generating Verilog with multiple instances of the
same module.
The new API resides in package chisel3.experimental.hierarchy. Please
see the hierarchy ScalaDoc, documentation, and tests for examples of
use.
Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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Previous incomplete fixes in #2023 and #2031.
The legality of a FIRRTL connection is determined by type and flow.
Chisel does not have access to true flow information. Previous fix
attempts tried to use ActualDirection as a stand-in for flow, but it is
incorrect in many cases. This new approach checks the flows of the
lvalue and rvalues in the connect and flips the connection if either
the lvalue cannot be a sink or the rvalue cannot be a source.
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This will be slightly slower as it involves converting from Chisel
modules to FIRRTL modules before turning them into Strings. This cost is
somewhat mitigated by doing that conversion lazily such that we never
materialize the entire firrtl Circuit in memory, only 1 module at a
time.
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Co-authored-by: Jack Koenig <koenig@sifive.com>
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(#1944)" (#2080)
This reverts commit ed894c61474c8bc73761a6c360ef9d14505d853b.
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* remove DefRegInit, change DefReg API with option defination.
* add error message
* use Option[RegInitIR].
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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DataView is a mechanism for "viewing" Scala objects as a subtype of
`Data`. Often, this is useful for viewing one subtype of `Data`, as
another. One can think about a DataView as a cross between a
customizable cast and an untagged union.
A DataView has a Target type `T`, and a View type `V`. DataView requires
that an implementation of `DataProduct` is available for Target types.
DataProduct is a type class that provides a way to iterate on `Data`
children of objects of implementing types.
If a DataView is provided for a type T to a type V, then the function
.viewAs[V] (of type T => V) is available. The object (of type T) returned
by .viewAs is called a "View" and can be used as both an rvalue and an
lvalue. Unlike when using an .asTypeOf cast, connecting to a "View" will
connect to the associated field or fields of the underlying Target.
DataView also enables .viewAsSupertype which is available for viewing
Bundles as a parent Bundle type. It is similar to .viewAs but requires
a prototype object of the Target type which will be cloned in order to
create the returned View. .viewAsSupertype maps between the
corresponding fields of the parent and child Bundle types.
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Co-authored-by: Jack Koenig <koenig@sifive.com>
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Co-authored-by: Jack Koenig <koenig@sifive.com>
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PR #2023 fixed a composition issue for chisel3 biconnects delegating to
FIRRTL partial connect when compatibility mode Bundles are elements of
chisel3 Bundles. It missed an important case though that caused
previously working code to break.
The bug is fixed by doing the automatic flipping for compatibility mode
Bundles that have "Input" as a direction in addition to those that are
"Flipped".
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This has been legal in FIRRTL since v1.2.3 (when reset inference started
using a unification-style algorithm) but was never exposed in the Chisel
API.
Also delete the overridden connects in AsyncReset and ResetType which
just duplicate logic from MonoConnect.
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BiConnect in chisel3 delegates to FIRRTL <- semantics whenever it hits a
Bundle defined in `import Chisel._`. Because chisel3 <> is commutative
it needs to be mindful of flippedness when emitting a FIRRTL <- (which
is *not* commutative).
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* Add @ekiwi's code as a starting point
* Add test for ChiselEnum isOneOf method
* Make isOneOfTester naming consistent with other testers
* Add scaladoc comments for isOneOf
* Add isOneOf tests that use the method that takes variable number of args
* Add guide level documentation example for isOneOf
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Change the Scaladoc for the dontTouch utility. Indicate that this is an
_optimization barrier_ and not just a guarantee that the signal won't be
removed. The optimization barrier interpretation is the current
implementation in the Scala FIRRTL Compiler.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Previously, ChiselEnum would warn any time a UInt is converted to an
Enum. There was no way to suppress this warning. Now there is a factory
method (`.safe`) that does not warn and returns (Enum, Bool) where the
Bool is the result of calling .isValid on an Enum object. The regular
UInt cast is also now smarter and will not warn if all bitvectors of the
width of the Enum are legal states.
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It also uses the same logger as the Builder so that if we ever refactor
that to be passed as an argument, it will be the same logger for both
Builder and warning reporting.
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Previously, CloneModuleAsRecord clones would result in the same
BaseModule object coming up multiple times when using APIs like
.instances, .collectDeep, and .getDeep. This was not the intended
behavior and can lead to very subtle bugs.
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* deprecate getPorts with modulePorts.
* add doc to fullModulePorts and update deprecation notes.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* prototype annotating verif constructs
* switch to final class
* name emissions
* moving BaseSim to experimental
* adding name tests
* fixing quotation escapes
* emitting names, but everything has a default name
* only name things with provided/suggested names
* name every BaseSim node
* removing msg, unused imports
* fixing file exist calls
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This PR provides for support for Vec literals. They can be one of two forms
Inferred:
```
Vec.Lit(0x1.U, 0x2.U)
```
or explicit:
```
Vec(2, UInt(4.W)).Lit(0 -> 0x1.U, 1 -> 0x2.U)
```
- Explicit form allows for partial, or sparse, literals.
- Vec literals can be used as Register initializers
- Arbitrary nesting (consistent with type constraints is allowed)
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The compiler plugin obviates the need for using stack traces to
determine outer objects in autoclonetype. When the plugin was used to
compile a given Bundle, it will no longer collect a stack trace upon
construction. This should have massive benefits to elaboration runtime.
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Not a Pokémon
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* Handle MemTypeBinding in Analog
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
* Fix stack trace trimming across ChiselStage
Fix bug in stack trace trimming behavior. Now, the following is what
happens:
1. The Builder, if catching accumulated errors, will now throw a
ChiselException with a Scala-trimmed Stack trace. Previously, this
would throw the full excpetion.
2. The Elaborate phase handles stack trace trimming. By default, any
Throwable thrown during elaboration will have its stack
trace *mutably* trimmed and is rethrown. A logger.error is printed
stating that there was an error during elaboration and how the user
can turn on the full stack trace. If the --full-stacktrace option
is on, then the Throwable is not caught and only the first
logger.error (saying that elaboration failed) will be printed.
3. ChiselStage (the class), ChiselStage$ (the object), and ChiselMain
all inherit the behavior of (2).
Mutable stack trace trimming behavior is moved into an implicit
class (previously this was defined on ChiselException only) so this
can be applied to any Throwable.
No StageErrors are now thrown anymore. However, StageErrors may still
be caught by ChiselMain (since it is a StageMain).
Testing is added for ChiselMain, ChiselStage, and ChiselStage$ to test
all this behavior.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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No longer create a pointer from parent to every HasId, only do it by
default for BaseModules and MemBases. Add pointer from parent to Data
upon binding the Data.
* Add MemTypeBinding for port types of Mems
This binding is similar to the SampleElementBinding for Vecs in that
these Data are not truly hardware, but are represented in the FIRRTL IR
and thus need some representation.
* Call _onModuleClose on unbound Records
This maintains some corner-case behavior that is nevertheless relied
upon. It ensures that refs are set for the elements of Records, even if
they are not bound to any real hardware.
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* Update reported width from div/rem to match FIRRTL results
* Add tests for width of % and / on UInt and SInt
* Add loop-based test for known UInt/SInt op result widths
Co-authored-by: Jack Koenig <koenig@sifive.com>
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This is a nit fix. no logic is changed.
* Rename `typeName` to `enumTypeName` in ScalaDoc
* Add return type at public method
* Rename `enum_records` into `enumRecords` to retain name consistency
Co-authored-by: Jack Koenig <koenig@sifive.com>
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Co-authored-by: Megan Wachs <megan@sifive.com>
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Chisel projects no longer need -Xsource:2.11 when compiling with Scala
2.12.
Autowrapping of "val io" for compatibility mode Modules is now
implemented using reflection instead of calling the virtual method.
Also move Chisel.BlackBox to new chisel3.internal.LegacyBlackBox
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This PR revert #1480, but keep the test.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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This is useful for libraries to guard operations implemented via
annotations or BlackBoxes by the current when predicate
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