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2022-03-10Emit FIRRTL bulkconnects whenever possible (#2381) (#2440)mergify[bot]
Chisel <> semantics differ somewhat from FIRRTL <= semantics, so we only emit <= when it would be legal. Otherwise we continue the old behavior of emitting a connection for every leaf-level Element. Co-authored-by: Deborah Soung <debs@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit 3553a1583403824718923a6cc530cec3b38f5704) Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-03-09Support BlackBoxes in D/I (#2438) (#2442)mergify[bot]
Also delete an errant println in InstanceSpec (cherry picked from commit 3462c54c018a52a377f1c89121b6ed99c5b0ae1d) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-03-04Issue errors on out-of-range extracts when width is known (#2428) (#2429)mergify[bot]
* Issue errors on out-of-range extracts when width is known Firrtl will catch this later on, but better to error early if possible. * Test that errors are generated on OOB extracts when width is known (cherry picked from commit 462def429aa87becb544533880a3075a806c53e4) Co-authored-by: Andrew Waterman <andrew@sifive.com>
2022-02-11Hierarchy API: make Mems lookupable (#2404) (#2410)mergify[bot]
(cherry picked from commit 2a985ac376698a2e6300fbee13001d82d3e13989) Co-authored-by: Deborah Soung <debs@sifive.com>
2022-02-10Make Tuple2 Lookupable (#2372) (#2406)mergify[bot]
(cherry picked from commit 024847d75079a125e5946e9dcf2ed9c14d2db730) Co-authored-by: Megan Wachs <megan@sifive.com>
2022-02-04Fix variable-name typo (#2397) (#2400)mergify[bot]
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit 015755749caa8a05f3809d446b023df80c7419d1) Co-authored-by: Tynan McAuley <tynan@galois.com>
2022-02-04Fix bundle elements performance regression (#2396) (#2398)mergify[bot]
* Only call _elementsImpl once in Bundle.elements * Distinguish compiler plugin and reflective _elementsImpl Bundle.elements now will only do post-processing if the user is using plugin-generated _elementsImpl. This improves performance for the case where the user does not opt-in to using the plugin to generate _elementsImpl. (cherry picked from commit 5fead89ee0132355e551bcb6b87cc2a6db679bee) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-02-03Tweak Bundle._elementsImpl (#2390) (#2392)mergify[bot]
* Change type of Bundle._elementsImpl to Iterable It was previously SeqMap (ListMap on Scala 2.12). This change gives us more freedom to optimize the implementation without breaking binary compatibility. It is scala.collection.Iterable because it is perfectly fine to return mutable collections (like Arrays) since the only use is to Iterate on them. * Disallow users implementing Bundle._elementsImpl Currently, it would result in a runtime linkage error. This turns it into a compile-time error. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit 1b05a14ad6d5784f3b91ab510dc1095423c23ea8) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-02-03Tweak new mem port clock warnings (#2389) (#2391)mergify[bot]
Use Builder.deprecated instead of Builder.warning so that the warnings are aggregated by source locator to prevent spamming the screen with duplicated warnings. (cherry picked from commit 538e223ae81c8b66a4123303f6dab61c874aaa1e) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-02-01Improve error reporting (backport #2376) (#2379)mergify[bot]
* Improve error reporting (#2376) * Do not trim stack traces of exceptions with no stack trace This prevents us from accidentally giving stack traces to exceptions that don't have them and giving misleading messages telling users to use --full-stacktrace when it won't actually do anything. Also deprecate ChiselException.chiselStackTrace which is no longer being used anywhere in this codebase. * Add exception class for multiple-errors reported New chisel3.internal.Errors replaces old anonymous class that would show up as chisel3.internal.ErrorLog$$anon$1 in error messages. * Add new option --throw-on-first-error This tells Chisel not to aggregate recoverable errors but instead to throw an exception on the first one. This gives a stack trace for users who need it for debugging. (cherry picked from commit ff2e9c92247b3848659fa09fdd53ddde2120036a) * Waive MiMa false positives The waived change is to a package private constructor. Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2022-02-01Optional clock param for memory ports (#2333) (#2382)mergify[bot]
Warn if clock at memory instantiation differs from clock bound at port creation and port clock is not manually passed Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit 465805ec7b2696a985eaa12cf9c6868f11ac2931) Co-authored-by: Aditya Naik <91489422+adkian-sifive@users.noreply.github.com>
2022-02-01Chisel plugin bundle elements handler (#2306) (#2380)mergify[bot]
Adds generation of `Bundle.elements` method to the chores done by the compiler plugin For each `Bundle` find the relevant visible Chisel field members and construct a hard-coded list of the elements and their names implemented as `_elementsImpl` For more details: See plugins/README.md - Should be no change in API - Handles inheritance and mixins - Handles Seq[Data] - Tests in BundleElementSpec Co-authored-by: chick <chick.markley@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit 237200a420581519f29149cbae9b3e968c0d01fc) Co-authored-by: Chick Markley <chick@qrhino.com>
2022-01-20Fix Compatibility Module io wrapping (#2355) (#2358)mergify[bot]
The new reflection based IO autowrapping for compatibility mode Modules would previously throw a NullPointerExceptions if any hardware were constructed in the Module before "val io" was initialized. The logic is now more robust for this case. Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> (cherry picked from commit 50e6099fbecc041973564514e55f67ffe069459b) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-01-11Lookupable: add Either version (#2335)Megan Wachs
* Add Lookupable for Either * Lookupable: enhance the @public/@instantiable error message to include traits and Eithers Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-01-10Apply scalafmtJack Koenig
Command: sbt scalafmtAll
2022-01-07Add a Select.ios that works with Definition/Instance, fix isA behavior (#2315)Megan Wachs
* New Feature: Add a Select.ios that works with Definition/Instance * BugFix: isA now truly ignores type parameters
2021-12-18Revert "Make stuff in IR.scala package private (#2274)" (#2308)Jack Koenig
This reverts commit 21e324727e99f0bc124aaddea7fe294b4111c23a. Note that I am keeping the change making Arg sealed.
2021-12-17Improve exception message for aliased bundle fields (#2304)Chick Markley
- Shows groups of field names that share a common id (i.e. aliased) - Show, as much as possible, them in the order that fields appear in bundle - Updated BundleSpec's relevant tests Co-authored-by: Megan Wachs <megan@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-12-15Restore Port to public API and deprecate (#2302)Jack Koenig
Also clean up deprecation warnings for replacement APIs and add clarifying ScalaDoc.
2021-12-15deprecate getModulePorts (#2284)Jiuyang Liu
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-12-14Make stuff in IR.scala package private (#2274)Aditya Naik
2021-12-11reduceTree() now operates on Seq (#2292)Øyvind Harboe
preserves input/output information of the type being reduced. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-12-10Add support for dynamic indexing on Vec identity views (#2298)Jack Koenig
2021-12-09Better MonoConnect error messages (#2248)Aditya Naik
Co-authored-by: Megan Wachs <megan@sifive.com>
2021-12-08Implement DataViews for Seq and Tuple (#2277)Jack Koenig
* DataProducts for Seq and Tuple2-10 in DataProduct companion object * DataViews for Seq and Tuple 2-10 in DataView companion object * HWTuple2-10 Bundles in chisel3.experimental * Implicit conversions from Seq to Vec and Tuple to HWTuple in chisel3.experimental.conversions
2021-12-02Refactor Data.toString (#2197)Aditya Naik
Provides a more intuitive implementation of toString for Data. Utilizes the fact that the compiler plugin provides names earlier than Chisel had in the past so we can accurately guess the name of signals even in the currently elaborating module. Co-authored-by: Megan Wachs <megan@sifive.com> Co-authored-by: Jack Koenig <jack.koenig3@gmail.com>
2021-12-01Require the chisel3 compiler plugin (#2271)Jack Koenig
As the chisel3 compiler plugin is now required, we can delete unused code for reflective autoclonetype as well as the noPluginTests.
2021-12-01Bugfix - definition name index skipping with D/I (#2249)Aditya Naik
* Bugfix - definition name index skipping with D/I * Add tests to DefinitionSpec * Add failing test * Fix failing test * Update core/src/main/scala/chisel3/internal/Builder.scala Co-authored-by: Jack Koenig <jack.koenig3@gmail.com> * whitespace * revert package private val Co-authored-by: Jack Koenig <jack.koenig3@gmail.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-11-14remove_toBoolsJiuyang Liu
2021-10-29Exposing more APIs from D/I internals (#2220)Adam Izraelevitz
Exposing more internals of D/I, which are required for supporting D/I with more powerful Chisel libraries: - Exposing IsClone[_] - Exposing InstantiableClone[_] - Gated builders for Instance/Definition - Unsealing Lookupable, with protected accessors for proto and cloned
2021-10-27Add Select APIs for Hierarchy package (#2210)Adam Izraelevitz
* Add Hierarchy trait * Add Hierarchy trait * Add Hierarchy scaladoc * Add license * Add isA and tests * Add back isA * Add new Select APIs for hierarchy package * Update scaladoc * Write outlines for tests * Add tests and fixes to new Select functions * Make calculate via lazy val * Apply suggestions from code review Co-authored-by: Megan Wachs <megan@sifive.com> * Apply suggestions from code review Co-authored-by: Megan Wachs <megan@sifive.com> * Clean up scaladoc * Add shouldNot compile * Apply suggestions from code review Co-authored-by: Megan Wachs <megan@sifive.com> * Bugfix all funcs should analyze root too * Add mdoc, bugfix toDefinition * Make func private, add scaladoc * Update src/test/scala/chiselTests/experimental/hierarchy/InstanceSpec.scala Co-authored-by: Jack Koenig <koenig@sifive.com> * Made protected vals private * Apply suggestions from code review Co-authored-by: Jack Koenig <koenig@sifive.com> * Address code review comments * Added additional null check Co-authored-by: Megan Wachs <megan@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-10-27Add java reflection to hierarchy (#2209)Adam Izraelevitz
* Add Hierarchy trait * Add Hierarchy trait * Add Hierarchy scaladoc * Add license * Add isA and tests * Add back isA * Make calculate via lazy val * Apply suggestions from code review Co-authored-by: Megan Wachs <megan@sifive.com> * Add shouldNot compile * Update src/test/scala/chiselTests/experimental/hierarchy/InstanceSpec.scala Co-authored-by: Jack Koenig <koenig@sifive.com> * Made protected vals private Co-authored-by: Megan Wachs <megan@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-10-25Bugfix: fix isACloneOf (#2205)Adam Izraelevitz
2021-10-25Add Hierarchy trait (#2204)Adam Izraelevitz
2021-10-20Update computeName and callsites (#2192)Aditya Naik
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-10-07Fixed bug with unary minus on FixedPoint and Interval (#2154)Chick Markley
In `Bits.scala`, `FixedPoint` and `Interval` did not defeine the `do_unary_-` methods (the `do_`) was missing The recent PR #2124 combined with the above fact made DspTools break. This fix is necessary to get that repo to build.
2021-10-05Circular-shift (rotate) operations for UInt (#1140)Kamyar Mohajerani
* change static shift behavior to mod width when width is known * add dynamic shift * basic tests that actually do something * MatchedRotateLeftAndRight based on the idea from @chick * BasicRotate rotate "b001" and compare with known values * Fix check for KnownWidth(0|1) as suggested by @aswaterman * Add dontTouch to UIntOps.io (other tests were also optimized out) Co-authored-by: Chick Markley <chick@qrhino.com> Co-authored-by: Andrew Waterman <andrew@sifive.com>
2021-10-05Fix naming of unwrapped val io in Chisel.Modules (#2150)Jack Koenig
The removal of virtual method io accidentally made the naming of io in compatibility mode Bundles sensitive to the prefix at the time of the first access of the field. It also made .suggestName able to override the name. This commit fixes that issue by forcing the name of the io Data to be "io" no matter what.
2021-10-05Deprecate auto-application of empty argument lists to parameterless ↵Jared Barocsi
functions (#2124) * Migrate nullary funcs to parameterless versions * Make deprecation message and dummy arguments clear and consistent Co-authored-by: Megan Wachs <megan@sifive.com>
2021-10-05Remove all Bundle cloneTypes and chiselRuntimeDeprecate its use (#2052)Megan Wachs
* Remove all manual cloneTypes and make it chisel runtime deprecated to add one * runtime deprecate cloneType with runtime reflection * [Backport this commit] Bundle: add check that override def cloneType still works (will be made an error later) * Plugin: make it an error to override cloneType and add a test for that * Docs: can't compile the cloneType anymore * BundleSpec: comment out failing test I cannot get to fail or ignore Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-10-05Remove v3.4.0 version of autoNameRecursively (#2149)Jack Koenig
2021-09-23make all verification statements publically available (#2089)Kevin Laeufer
2021-09-21implement trace API. (#2077)Jiuyang Liu
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-09-08Restore return type of BaseModule.toTarget to ModuleTarget (#2117)Jack Koenig
Definition/Instance introduced the need for representing the targets of instances as InstanceTargets. This original implementation changed the return type of BaseModule.toTarget to express this need. This is a backwards incompatible change that is actually unnecessary because it is impossible for users to get references to the internal InstanceClone objects, instead only accessing such modules via Instance[_] wrappers and cloned Data. We restored the old API by adding a new internal method "getTarget" which will give the correct targets for InstanceClones while maintaining the API of BaseModule.toTarget.
2021-09-05Add Definition and Instance API (#2045)Adam Izraelevitz
This introduces a new experimental API for module instantiation that disentagles elaborating the definition (or implementation) from instantiation of a given module. This solves Chisel's longstanding reliance on "Deduplication" for generating Verilog with multiple instances of the same module. The new API resides in package chisel3.experimental.hierarchy. Please see the hierarchy ScalaDoc, documentation, and tests for examples of use. Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: Megan Wachs <megan@sifive.com> Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-08-31Fix chisel3 <> for compatibility Bundles (Take 3) (#2093)Jack Koenig
Previous incomplete fixes in #2023 and #2031. The legality of a FIRRTL connection is determined by type and flow. Chisel does not have access to true flow information. Previous fix attempts tried to use ActualDirection as a stand-in for flow, but it is incorrect in many cases. This new approach checks the flows of the lvalue and rvalues in the connect and flips the connection if either the lvalue cannot be a sink or the rvalue cannot be a source.
2021-08-30SyncReadMem: fix bug with read(addr) and add some formal tests (#2092)Kevin Laeufer
2021-08-23Remove chisel3's own firrtl Emitter, use firrtl SerializerJack Koenig
This will be slightly slower as it involves converting from Chisel modules to FIRRTL modules before turning them into Strings. This cost is somewhat mitigated by doing that conversion lazily such that we never materialize the entire firrtl Circuit in memory, only 1 module at a time.
2021-08-23Add multiple dimensions to VecInit fill and iterate (#2065)anniej-sifive
Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-08-18Builder: downgrade "Elaborating design" message to info (#2081)Kevin Laeufer
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