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2022-08-16Add OpaqueType support to Records (backport #2662) (#2679)mergify[bot]
* Add OpaqueType support to Records (#2662) OpaqueTypes are essentially type aliases that hide the underlying type. They are implemented in Chisel as Records of a single, unnamed element where the wrapping Record does not exist in the emitted FIRRTL. Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit df5afee2d41b5bcd82d4013b977965c0dfe046fd) * Fix test compilation * Fix OpaqueType tests in RecordSpec Need to implement cloneType correctly and to warn instead of error when accessing .toTarget of non-hardware types because that is a warning (not error) in 3.5. * Waive MiMa false positives Co-authored-by: Aditya Naik <91489422+adkian-sifive@users.noreply.github.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-08-16Add a cookbook and publicly visible scaladoc for prefix, noPrefix (#2687) ↵mergify[bot]
(#2690) * Add a cookbook and publicly visible scaladoc for prefix, noPrefix (cherry picked from commit ae7dc30b3b99f1fbd91c35f54bc19be7c55f74a3) Co-authored-by: Megan Wachs <megan@sifive.com>
2022-08-16Privatize trait VerifPrintMacros (#2683) (#2685)mergify[bot]
(cherry picked from commit de76e70bc5905fc4ebc8a2e323e16620fa6832ec) Co-authored-by: Aditya Naik <91489422+adkian-sifive@users.noreply.github.com>
2022-08-15Printables for verification preconditions (backport #2663) (#2680)mergify[bot]
* Printables for verification preconditions (#2663) Add support for printable within assert and assume verification statements Co-authored-by: Girish Pai <girish.pai@sifive.com> Co-authored-by: Megan Wachs <megan@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit 7df5653309b5e48e1732b335610d9a7e8449f903) * Waive MiMa false positive Co-authored-by: Aditya Naik <91489422+adkian-sifive@users.noreply.github.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-08-13Add option to treat warnings as errors (backport #2676) (#2677)mergify[bot]
* Add option to treat warnings as errors (#2676) Add --warnings-as-errors option (cherry picked from commit 498946663726955c380a1e420f5d7b9630000aad) # Conflicts: # core/src/main/scala/chisel3/experimental/hierarchy/Definition.scala # core/src/main/scala/chisel3/internal/Builder.scala # src/main/scala/chisel3/aop/injecting/InjectingAspect.scala # src/main/scala/chisel3/stage/ChiselOptions.scala # src/main/scala/chisel3/stage/package.scala # src/main/scala/chisel3/stage/phases/Elaborate.scala * Resolve backport conflicts Co-authored-by: Zachary Yedidia <zyedidia@gmail.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-08-12Show equivalent warnings/errors only once (#2673) (#2675)mergify[bot]
(cherry picked from commit ae76ff4cb303a6646e48dc044be47051b67e7cbb) Co-authored-by: Zachary Yedidia <zyedidia@gmail.com>
2022-08-12Add ability to suppress enum cast warnings (#2671) (#2674)mergify[bot]
(cherry picked from commit 1ad820f7f549eddcd7188b737f59a240e48a7f0a) Co-authored-by: Zachary Yedidia <zyedidia@gmail.com>
2022-08-05Replace some options with nullable vars (backport #2658) (#2659)mergify[bot]
* Replace some options with nullable vars (#2658) Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit ac460bfeb16c8e7d0dc00975bb03f73c0fea2103) # Conflicts: # core/src/main/scala/chisel3/internal/Builder.scala * Fix backport conflicts (#2661) Co-authored-by: Zachary Yedidia <zyedidia@gmail.com>
2022-07-22ChiselEnum: make factory package private (#2639) (#2640)mergify[bot]
This is required in order to support peeks in chiseltest. (cherry picked from commit 26cd15a9943ca20829630d2feedac08a069291c2) Co-authored-by: Kevin Laeufer <laeufer@cs.berkeley.edu>
2022-07-21Deprecate chiselName and NoChiselNamePrefix trait (#2627) (#2633)mergify[bot]
Also remove all non-testing uses of chiselName. (cherry picked from commit 1c5d1b5317a0c9fe7ef9d15138065a817380a1e4) Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
2022-07-143.5x: Make explicit copy constructors for ExplicitCompileOptions (#2629)Megan Wachs
* Add copy constructors for compile options * Add tests for the copy constructors Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
2022-07-13New enhanced API for specifying Chisel to Firrtl Annotations (#2628) (#2631)mergify[bot]
(cherry picked from commit 4b10cf7a276e90b280c1fd57070566acac3d80d3) Co-authored-by: Girish Pai <girish.pai@sifive.com>
2022-07-08CompileOptions: add and use emitStrictConnects (#2622) (#2623)mergify[bot]
(cherry picked from commit 11e8cc60d6268301cff352b8a1d7c4d672b5be11) Co-authored-by: Megan Wachs <megan@sifive.com>
2022-07-06Implement trait for Chisel compiler to name arbitrary non-Data types (#2610) ↵mergify[bot]
(#2617) Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: Megan Wachs <megan@sifive.com> (cherry picked from commit 3ab34cddd8b87c22d5fc31020f10ddb2f1990d51) Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
2022-06-23Add DataMirror isIO, isReg, isWire (#2601) (#2602)mergify[bot]
(cherry picked from commit 7fa0d8bf1cafcdf141046476a100abf021bdcac4) Co-authored-by: Zachary Yedidia <zyedidia@gmail.com>
2022-06-22Pass optional name in ImportDefinitionAnno (#2592) (#2594)mergify[bot]
Used for separate elaboration of Definition and Instance (cherry picked from commit 48d57cc8db6f38fdf0e23b7dce36caa404c871b8) Co-authored-by: Girish Pai <girish.pai@sifive.com>
2022-06-16Define leading '_' as API for creating temporaries (backport #2580) (#2581)mergify[bot]
* Define leading '_' as API for creating temporaries Chisel and FIRRTL have long used signals with names beginning with an underscore as an API to specify that the name does not really matter. Tools like Verilator follow a similar convention and exclude signals with underscore names from waveform dumps by default. With the introduction of compiler-plugin prefixing in Chisel 3.4, the convention remained but was hard for users to use unless the unnnamed signal existed outside of any prefix domain. Notably, unnamed signals are most useful when creating wires inside of utility methods which almost always results in the signal ending up with a prefix. With this commit, Chisel explicitly recognizes signals whos val names start with an underscore and preserve that underscore regardless of any prefixing. Chisel will also ignore such underscores when generating prefixes based on the temporary signal, preventing accidental double underscores in the names of signals that are prefixed by the temporary. (cherry picked from commit bd94366290886f3489d58f88b9768c7c11fa2cb6) * Remove unused defaultPrefix argument from _computeName (cherry picked from commit ec178aa20a830df2c8c756b9e569709a59073554) # Conflicts: # core/src/main/scala/chisel3/Module.scala # core/src/main/scala/chisel3/experimental/hierarchy/ModuleClone.scala * Resolve backport conflicts * Waive false positive binary compatibility errors Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-06-13Add ImplicitInvalidate, to help migrate the explicitInvalidate compiler ↵mergify[bot]
option (#2575) (#2579) * Added ImplicitInvalidate trait with tests (cherry picked from commit 1356ced1b89ca35ae0cb1d1ab45227ec1776d5e7) Co-authored-by: Adam Izraelevitz <adam.izraelevitz@sifive.com>
2022-06-08Added migration for inferModuleReset (#2571) (#2573)mergify[bot]
Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit 3c6c044b6bdee850ad9ba375324abaf3813c557d) Co-authored-by: Adam Izraelevitz <adam.izraelevitz@sifive.com>
2022-06-07Add single argument Bits.extract (#2566) (#2568)mergify[bot]
(cherry picked from commit 255c56c3955a8c16191a6751e7d547cfcfd96705) Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
2022-06-06Add --warn:reflective-naming (backport #2561) (#2565)mergify[bot]
* Factor buildName into reusable function The new function is chisel3.internal.buildName. (cherry picked from commit 370ca8ac68f6d888dd99e1b9e63f0371add398cf) * Add --warn:reflective-naming This new argument (and associated annotation) will turn on a warning whenever reflective naming changes the name of a signal. This is provided to help migrate from Chisel 3.5 to 3.6 since reflective naming is removed in Chisel 3.6. (cherry picked from commit 97afd9b9a1155fa7cd5cedf19f9e0c15fbe899ec) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-06-03Deprecate implicit .U() and .S() syntax for literal bit extracts (backport ↵mergify[bot]
#2534) (#2559) * Deprecate .U() and .S() syntax for literal bit extracts (#2534) (cherry picked from commit cadaf33a650ef898fdab2f81244e4ad6a07a9ea8) # Conflicts: # macros/src/main/scala/chisel3/internal/sourceinfo/SourceInfoTransform.scala * Fix backport conflict (#2560) Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
2022-06-01Add formatted Printable interpolator `cf` (#2528) (#2553)mergify[bot]
This is a formatted version of the p"..." interpolator analogous to Scala's f"..." interpolator. The primary difference is that it supports formatting interpolated variables by following the variable with "%<specifier>". For example: printf(cf"myWire = $myWire%x\n") This will format the hardware value "myWire" as a hexidecimal value in the emitted Verilog. Note that literal "%" must be escaped as "%%". Scala types and format specifiers are supported and are handled in the same manner as in standard Scala f"..." interpolators. (cherry picked from commit 037f7b2ff3a46184d1b82e1b590a7572bfa6a76b) Co-authored-by: Girish Pai <girish.pai@sifive.com>
2022-05-29Deprecate accessing the name of non-hardware Data (#2550) (#2552)mergify[bot]
This includes (and is tested) for both the old .*Name APIs and .toTarget (cherry picked from commit 6e0d8d6b12e9d8f94c2cc43b92b2366ec70dfd50) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-05-27Make ExtModule port naming consistent with Module (#2548) (#2549)mergify[bot]
ExtModule now uses the same namePorts implementation as regular Modules. Previously, ExtModules only allowed port naming via runtime reflection. This meant that .suggestName and other naming APIs do not work. It also breaks FlatIO for ExtModule which is a potential replacement API for BlackBox's special `val io` handling. (cherry picked from commit 83cccfb782d9141bf2c843246c2a525c62392924) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-05-24Support Vecs of empty Bundles (#2543) (#2545)mergify[bot]
(cherry picked from commit a1e3a6b5324997864168111bee8c02a60abb0acc) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-05-19Support := views to DontCare (#2536) (#2539)mergify[bot]
(cherry picked from commit 77a6c93592d5766d66f199720fc6d69478005091) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-05-12Support separately elaborating definition and instance in ChiselStage ↵mergify[bot]
(backport #2512) (#2520) * Support separately elaborating definition and instance in ChiselStage (#2512) (cherry picked from commit a0aa4d1550e3fbde199a98529cffeb176fb4bed8) # Conflicts: # core/src/main/scala/chisel3/experimental/hierarchy/Definition.scala # core/src/main/scala/chisel3/experimental/hierarchy/Instance.scala # core/src/main/scala/chisel3/internal/Builder.scala * fixing imports (#2522) Co-authored-by: Deborah Soung <debs@sifive.com>
2022-04-25Fix error message for BlackBox without val io <: Record (#2504) (#2505)mergify[bot]
(cherry picked from commit f9aee1f72744abc6ee13aafc4d1a51a2783cbab8) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-04-20Generate a balanced tree with reduceTree (#2318) (#2499)mergify[bot]
The difference in logic depth for various paths now has a maximum of 1. Also make treeReduce order the same for 2.12 and 2.13 .grouped(_) returns an Iterator .toSeq on an Iterator returns a Stream in 2.12 and a List in 2.13 This can lead to changes in order when bumping from 2.12 to 2.13 that can be avoided by simply using an eager collection explicitly. Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit 6975f77f3325dec46c613552eac663c29011a67c) Co-authored-by: Martin Schoeberl <martin@jopdesign.com>
2022-04-19Allow creating memories without an implicit clock (#2494) (#2495)mergify[bot]
Fixes #2470 (cherry picked from commit 44165a259bb16733a41798edca6b554b13f1d54a) Co-authored-by: Kevin Laeufer <laeufer@cs.berkeley.edu>
2022-04-19verification: switch order of assert/assume and printf (#2484) (#2493)mergify[bot]
This is a quick fix for issue #2408 (cherry picked from commit d4ef9a96c4131252a0a49002a28be3391eb67258) Co-authored-by: Kevin Laeufer <laeufer@cs.berkeley.edu>
2022-04-18Fix small typos in doc comment (#2490) (#2492)mergify[bot]
(cherry picked from commit 52165fe2796d08c664069c148868aedc64ea3777) Co-authored-by: Lucheng Zhang <79909456+geekLucian@users.noreply.github.com>
2022-04-18Clarify example in Printable (#2454) (#2456)mergify[bot]
(cherry picked from commit d6a357d29cfa7120b3c0c90684b33be1863e5599) Co-authored-by: Megan Wachs <megan@sifive.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2022-04-15Enable Clock Invalidation (#2485) (#2487)mergify[bot]
Loosen restrictions on clocks to enable them to be connected to DontCare, i.e., be invalidated. Co-authored-by: Jack Koenig <koenig@sifive.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit 5d8a0c8e406376f7ceda91273fb0fa7a646865aa) Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2022-04-12Optimize memory use of naming prefixes (#2471) (#2480)mergify[bot]
* Use a single field instead of two in HasId (4-bytes per HasId) * Set the prefix to Nil after setting ref to free up memory Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit 3aa179f0dc1a29403fd25be7d3dc08630976d018) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-04-12Enhance views to [sometimes] support dynamic indexing and implement FlatIO ↵mergify[bot]
(backport #2476) (#2479) * Capture 1:1 mappings of Aggregates inside of views This is implemented by including any corresponding Aggregates from the DataView.mapping in the AggregateViewBinding.childMap (which is now of type Map[Data, Data]). This enables dynamically indexing Vecs that are themselves elements of larger Aggregates in views when the corresponding element of the view is a Vec of the same type. It also increases the number of cases where a single Target can represent part of a view. (cherry picked from commit 1f6b1ca14ccf86918065073c3f6f3626dd83a68e) * Add FlatIO API for creating ports from Bundles without a prefix (cherry picked from commit 772a3a1fe3b9372b7c2d7cd2d424b2adcd633cdb) * [docs] Add FlatIO to the general cookbook (cherry picked from commit b4159641350f238f0f899b69954142ce8ee11544) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-04-05Micro-optimize Namespace.name (#2474) (#2475)mergify[bot]
* During sanitize, only filter the String if needed * Do not recurse on name, saving an unnecessary call to sanitize (cherry picked from commit 559b3df3e5bd6c73588638aa44a6df1244a11a53) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-04-05Micro-optimize String building in _computeName (#2472) (#2473)mergify[bot]
(cherry picked from commit 3940136bec72fc44e40d454f2c2dcc421fc92d82) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-04-01Prevent FIRRTL bulk connects on BlackBox Bundles. (#2468) (#2469)mergify[bot]
(cherry picked from commit 4da1e89f3a0b79adcb39ea5defb393ed6c00fa2f) Co-authored-by: fzi-hielscher <47524191+fzi-hielscher@users.noreply.github.com>
2022-03-30Use var List instead of ListBuffer to save memory (#2465) (#2467)mergify[bot]
This reduces memory use of every HasId by 64 bytes. Every instance of HasId (including all Data) had 2 ListBuffer vals for recording post-naming hooks, yet this feature is almost never used. These are now vars of type List which allows the common case of Nil to add no incremental memory use per instance of HasId. (cherry picked from commit cf410180ac8de854d8d7ecf89f4813ac8541dcdb) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-03-10Emit FIRRTL bulkconnects whenever possible (#2381) (#2440)mergify[bot]
Chisel <> semantics differ somewhat from FIRRTL <= semantics, so we only emit <= when it would be legal. Otherwise we continue the old behavior of emitting a connection for every leaf-level Element. Co-authored-by: Deborah Soung <debs@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com> (cherry picked from commit 3553a1583403824718923a6cc530cec3b38f5704) Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-03-09Support BlackBoxes in D/I (#2438) (#2442)mergify[bot]
Also delete an errant println in InstanceSpec (cherry picked from commit 3462c54c018a52a377f1c89121b6ed99c5b0ae1d) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-03-04Issue errors on out-of-range extracts when width is known (#2428) (#2429)mergify[bot]
* Issue errors on out-of-range extracts when width is known Firrtl will catch this later on, but better to error early if possible. * Test that errors are generated on OOB extracts when width is known (cherry picked from commit 462def429aa87becb544533880a3075a806c53e4) Co-authored-by: Andrew Waterman <andrew@sifive.com>
2022-02-11Hierarchy API: make Mems lookupable (#2404) (#2410)mergify[bot]
(cherry picked from commit 2a985ac376698a2e6300fbee13001d82d3e13989) Co-authored-by: Deborah Soung <debs@sifive.com>
2022-02-10Make Tuple2 Lookupable (#2372) (#2406)mergify[bot]
(cherry picked from commit 024847d75079a125e5946e9dcf2ed9c14d2db730) Co-authored-by: Megan Wachs <megan@sifive.com>
2022-02-04Fix variable-name typo (#2397) (#2400)mergify[bot]
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit 015755749caa8a05f3809d446b023df80c7419d1) Co-authored-by: Tynan McAuley <tynan@galois.com>
2022-02-04Fix bundle elements performance regression (#2396) (#2398)mergify[bot]
* Only call _elementsImpl once in Bundle.elements * Distinguish compiler plugin and reflective _elementsImpl Bundle.elements now will only do post-processing if the user is using plugin-generated _elementsImpl. This improves performance for the case where the user does not opt-in to using the plugin to generate _elementsImpl. (cherry picked from commit 5fead89ee0132355e551bcb6b87cc2a6db679bee) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-02-03Tweak Bundle._elementsImpl (#2390) (#2392)mergify[bot]
* Change type of Bundle._elementsImpl to Iterable It was previously SeqMap (ListMap on Scala 2.12). This change gives us more freedom to optimize the implementation without breaking binary compatibility. It is scala.collection.Iterable because it is perfectly fine to return mutable collections (like Arrays) since the only use is to Iterate on them. * Disallow users implementing Bundle._elementsImpl Currently, it would result in a runtime linkage error. This turns it into a compile-time error. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit 1b05a14ad6d5784f3b91ab510dc1095423c23ea8) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-02-03Tweak new mem port clock warnings (#2389) (#2391)mergify[bot]
Use Builder.deprecated instead of Builder.warning so that the warnings are aggregated by source locator to prevent spamming the screen with duplicated warnings. (cherry picked from commit 538e223ae81c8b66a4123303f6dab61c874aaa1e) Co-authored-by: Jack Koenig <koenig@sifive.com>
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