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And more changes
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RawModule will require major reworking in the future
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35 erros
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* Promote ChiselEnum user APIs from experimental (#2929)
They are commonly used and if we were ever to change them, we will need
to go through a deprecation process anyway.
Note that the EnumAnnotations remain in chisel3.experimental because,
like all Chisel annotation support, they are slated to be deprecated and
removed.
(cherry picked from commit 424e9446f1675fe0168e22bdfbbe85db997376e6)
# Conflicts:
# docs/src/cookbooks/verilog-vs-chisel.md
# docs/src/explanations/chisel-enum.md
* Maintain binary compatbility, use aliases in chisel3 package
* Deprecate the actual classes in chisel3.experimental
* Also fix backport conflicts
Co-authored-by: Jack Koenig <koenig@sifive.com>
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#2907) (#2928)
* Check for Vec subaccess in NamedComponent and throw a nicer error. (#2907)
This would previously end up throwing an exception later, when trying
to create a component name and realizing that it was invalid. Instead,
this detects Vec subaccesses early, and gives a more precise error and
suggestion.
(cherry picked from commit d8c30961c7b293ee19024a487698630367ee71c6)
# Conflicts:
# core/src/main/scala/chisel3/internal/Builder.scala
* Resolve backport conflicts
Co-authored-by: Mike Urbach <mikeurbach@gmail.com>
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ChiselEnums check if they should create annotations every time an
instance of them is bound. Because so many annotations would be created,
they check to see if an equivalent annotation has already been added to
the annotations. Previously, this used a linear search of the
annotations, now it uses a HashSet.
(cherry picked from commit 96bde092e449281dc70ebdb05f21695468c3e5fa)
Co-authored-by: Jack Koenig <koenig@sifive.com>
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Co-authored-by: Aditya Naik <aditya.naik@sifive.com>
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* Make PriorityMux stack safe (#2854)
It used to be implemented with recursion, now it's implemented with a
stack safe reverse and foldLeft.
Also there were no tests for PriorityMux so I added one which helps
prove the change is functionally correct.
(cherry picked from commit 269ce472e9aa0c242fc028871a1fd5b045c82f83)
# Conflicts:
# src/test/scala/chiselTests/util/PipeSpec.scala
* Resolve backport conflicts
Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* Implement compressed Namespace (#2856)
The namespace disambiguates requests for the same name with _<idx>.
Rather than storing every disambiguated name in the underlying HashMap,
it now only stores the base along with the "next available" index. This
makes the logic for checking if a name is already contained in the
namespace slightly more sophisticated because users can name things in a
way that will collide with disambiguated names from a common substring.
For example, in naming the sequence "foo", "foo", "foo_1", the 2nd "foo"
takes the name "foo_1" so the following "foo_1" gets disambiguated to
"foo_1_1". But since we compressed that original "foo_1" into the same
HashMap entry as just "foo", we have to do a form of "prefix checking"
whenever naming something that ends in "_<idx>".
In practice, the saved memory allocations more than make up for the more
complicated logic to disambiguate names because the common case is still
fast.
(cherry picked from commit 1654d87a02ca799bf12805a611a91e7524d49843)
# Conflicts:
# core/src/main/scala/chisel3/internal/Builder.scala
* Resolve backport conflicts
Co-authored-by: Jack Koenig <koenig@sifive.com>
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(cherry picked from commit 49feb083c69066988ca0666ea4249a86570e2589)
Co-authored-by: Megan Wachs <megan@sifive.com>
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* Change RawModule._commands to a VectorBuilder (#2839)
* Change RawModule._commands to a VectorBuilder
Use the resulting Vector to build the underlying Component's commands
and then use those instead of copying the original ArrayBuffer when
iterating on commands. Previously, the Component was using a List to
hold the commands which is particularly memory inefficient, especially
for large modules.
* Optimize Converter's handling of Seq[Command]
It previously converted the Commands to a List (which, while not
captured in the type system, they were already a List) and then used
head and tail iteration. This is less efficient with the new underlying
Vector implementation.
(cherry picked from commit 48a1ef0a3872c6b68d46145764d977926923a270)
* Waive false binary compatibility failures
Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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(#2757)
* Add internal methods to maintain binary compatibility
Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
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#2792) (#2834)
* Fixup and unit tests for D/I of IOs without explicit Input/Output (#2792)
(cherry picked from commit f24a624863f0fc460fd862238688ea8612ffdf5e)
# Conflicts:
# core/src/main/scala/chisel3/Module.scala
* Resolve backport conflicts
Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
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* Unify Chisel2 and chisel3 directionality (#2634)
Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit 1aea4ef96466cbe08150d20c85c88b81e4e4f80f)
# Conflicts:
# core/src/main/scala/chisel3/Aggregate.scala
# core/src/main/scala/chisel3/Module.scala
# src/test/scala/chiselTests/Direction.scala
* fix up backport
* fix up backport
* clean up diff
* make test order like it was on master
Co-authored-by: Adam Izraelevitz <adam.izraelevitz@sifive.com>
Co-authored-by: Megan Wachs <megan@sifive.com>
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* Switch to using experimental trait for OpaqueTypes (#2783)
This makes it more clear that the feature is experimental. Users may
still override the opaqueType method for more dynamic control over when
instances of a given Record are OpaqueTypes or not, but they are
discouraged from doing so.
(cherry picked from commit 7525dc71ccc2050d8e4a68b38f3b76920ba693fc)
* Fix cloneType in RecordSpec
Co-authored-by: Jack Koenig <koenig@sifive.com>
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#2829) (#2831)
* Add Aggregate.elementsIterator and micro-optimize
elementsIterator provides a more efficient API for iterating on the
elements of Aggregates. It is especially useful for Records where
getElements returns a Seq and thus eagerly constructs a new
datastructure which may then just be iterated on anyway.
This new elementsIterator API is then used throughout the codebase where
it makes sense.
Also change Vec.getElements to just return the underlying self instead
of constructing a new Seq.
(cherry picked from commit defa440b349031475daeff4024fad04925cccee6)
# Conflicts:
# core/src/main/scala/chisel3/Aggregate.scala
# core/src/main/scala/chisel3/Module.scala
# core/src/main/scala/chisel3/experimental/Trace.scala
* Move Aggregate.bind inline into Record.bind
Vec overrides bind and does not call the version in Aggregate so the
version in Aggregate is misleading in that its only ever used by
Records. Now there is no version in Aggregate and the actual
functionality and use is more clear.
(cherry picked from commit b054c30ba47026cb2a9b28c696a0a0a58b1e2ee7)
# Conflicts:
# core/src/main/scala/chisel3/Aggregate.scala
* Extract and optimize duplicate checking Record.bind
This replaces an immutable.Map with a single mutable.HashSet and saves
the allocation of # elements Seqs.
(cherry picked from commit 832ea52bc23424bb75b9654422b725a9cafaef40)
# Conflicts:
# core/src/main/scala/chisel3/Aggregate.scala
* Add check for Records that define def elements
(cherry picked from commit a4f223415de19e2a732e0b6a8fe681f706a19a56)
* Resolve backport conflicts
* Make elementsIterator final and package private
* Waive false MiMa failure
Co-authored-by: Jack Koenig <koenig@sifive.com>
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* Bugfix converter clearing flips (#2788)
* Bugfix: Output on Vec of bundle with mixed field orientations
* Bugfix OpaqueTypes clearing flips
(cherry picked from commit f05bff1a337589bafebd08783bb0f6a72092a95a)
# Conflicts:
# src/test/scala/chiselTests/Direction.scala
* Resolve backport conflicts
Co-authored-by: Adam Izraelevitz <adam.izraelevitz@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
(cherry picked from commit fce8394bb0ddc9ae0d9c6668e034e483bd6b71c5)
Co-authored-by: Jack Koenig <koenig@sifive.com>
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Co-authored-by: Megan Wachs <megan@sifive.com>
(cherry picked from commit 26100a875c69bf56f7442fac82ca9c74ad3596eb)
Co-authored-by: Jack Koenig <koenig@sifive.com>
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* Add PartialDataView.supertype (#2826)
This factory method makes it easy to create PartialDataViews from a
Bundle type to its supertype. Because of the typing relationship, there
is no need to provide a mapping between fields. The only thing necessary
is to provide a function for constructing an instance of the supertype
from an instance of the subtype.
(cherry picked from commit 251d454a224e5a961438ba0ea41134d7da7a5992)
# Conflicts:
# core/src/main/scala/chisel3/experimental/dataview/package.scala
# src/test/scala/chiselTests/experimental/DataView.scala
* Resolve backport conflicts
Co-authored-by: Jack Koenig <koenig@sifive.com>
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MonoConnect.traceFlow now properly handles coerced directions.
Also minor improvement to getClassName especially useful in test case printf debugging.
(cherry picked from commit 3aba755bdcf996c0fbd846d13268fd6641b29e96)
Co-authored-by: Megan Wachs <megan@sifive.com>
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(backport #2795) (#2799)
* Don't invalidate ExtModule ports in an explicitInvalidate = true context (#2795)
* Don't invalidate ExtModule ports in an explicitInvalidate = true context
ExtModule ports were previously invalidated in the emitted FIRRTL, which is correct in a NonStrict / `Chisel._` compatibility context but not in newer chisel3 code where `explicitInvalidate = true`.
(cherry picked from commit 8e24a281545d25f6501dcc872eabdfb30bacd69d)
# Conflicts:
# core/src/main/scala/chisel3/BlackBox.scala
* Resolve backport conflicts
Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
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(backport #2789) (#2790)
* Only set the chisel3 Builder prefix during the first invocation of suggestName
(cherry picked from commit b684506abab2f7b99d56181d548cb8119d317323)
# Conflicts:
# core/src/main/scala/chisel3/internal/Builder.scala
* Add simple test to show bug fix
(cherry picked from commit 255068b105de77a045a0016e3a157b52a81c86d6)
* Fix merge conflict
* Fix test to not use Hardware inside a bundle for prefixing
Co-authored-by: Jared Barocsi <jared.barocsi@sifive.com>
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Add utilities to enable backwards compatibility of the Trace.traceName
API to Chisel 3.5.x. This adds a Trace.traceNameV2 utility which
aliases to Trace.traceName. This also removes the TraceNameAnnotation
and renames it TraceAnnotation. In 3.5.x, traceName will point at
TraceNameAnnotation (which has don't touch behavior) and will be
deprecated telling people to use traceNameV2 which will point at
TraceAnnotation (which does not have don't touch behavior). This will
require fixups to the backport associated with this PR.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
(cherry picked from commit 47b7227e1ac7ccb0d48cefef03510542cc7e157e)
# Conflicts:
# core/src/main/scala/chisel3/experimental/Trace.scala
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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* Add opt-in AutoCloneType for Records (#2781)
There is a new trait, chisel3.experimental.AutoCloneType that is mixed
in to Bundle and can optionally be mixed in to user-defined Records. The
compiler plugin prints a deprecation warning on any user-defined
implementation of cloneType, telling the user to mix in AutoCloneType
before upgrading to 3.6.
(cherry picked from commit a234fd48ac8f5942c38fef5797292014e407b586)
# Conflicts:
# core/src/main/scala/chisel3/Aggregate.scala
# plugin/src/main/scala/chisel3/internal/plugin/BundleComponent.scala
* Resolve backport conflicts
* Do not make MixedVec extend AutoCloneType
It is a binary incompatible change that can wait for 3.6.
* Waive MiMa false positives
Co-authored-by: Jack Koenig <koenig@sifive.com>
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* Fix traceName module type to RawModule (#2765)
Change the type of modules that the traceName API can be used for from
"Module" to "RawModule". This fixes a bug where this API couldn't be
used for RawModules even though it totally works.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
(cherry picked from commit 74f1c85060cc72ebffe59a49f8d4539a464a4a19)
* Fix binary compatibility issue
Co-authored-by: Jack Koenig <koenig@sifive.com>
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* Add unit test for Issue 2760
* checkpoint: Fix for nested instance
* remove comments about stuff not working
* make the test check the output a little more
* relax the requirement on returning empty ioMap
* Update core/src/main/scala/chisel3/experimental/hierarchy/core/Lookupable.scala
* Update core/src/main/scala/chisel3/Data.scala
* Update core/src/main/scala/chisel3/experimental/hierarchy/core/Lookupable.scala
Co-authored-by: Jack Koenig <koenig@sifive.com>
* Update src/test/scala/chiselTests/experimental/hierarchy/InstanceSpec.scala
Co-authored-by: Jack Koenig <koenig@sifive.com>
* Update core/src/main/scala/chisel3/experimental/hierarchy/core/Lookupable.scala
* Add another unit test which unfortunately still passes
* Update core/src/main/scala/chisel3/Data.scala
* Update src/test/scala/chiselTests/experimental/hierarchy/InstanceSpec.scala
Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
(cherry picked from commit 1f9f26dc2bffcb4cc4daf2dc16c5cb455c6769ef)
Co-authored-by: Megan Wachs <megan@sifive.com>
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(cherry picked from commit 0ff99ca8d573e3487ef496a21c95d962689c3cba)
Co-authored-by: Aditya Naik <91489422+adkian-sifive@users.noreply.github.com>
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(cherry picked from commit f462c9f9307bebf3012da52432c3729cd752321c)
Co-authored-by: Aditya Naik <91489422+adkian-sifive@users.noreply.github.com>
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Referenced to: chipsalliance/chisel3#2728
(cherry picked from commit a4dae9c340c71c063cf0fdec290a6e011b82746d)
Co-authored-by: Marco Origlia <30799310+moriglia@users.noreply.github.com>
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* Remove incorrect clock warning on Mem.read (#2721)
Mem.read is combinational and thus unaffected by the clock, and so it
does not make sense to issue warnings about the current clock in this
context.
(cherry picked from commit 5fdf74f95e64cb69d6097547f20d789a83dbd735)
* Keep old version of MemBase.clockWarning for binary compatibility
This method is impossible for users to call, but it is easy enough to
keep around a version of it to make MiMa happy.
Co-authored-by: Andrew Waterman <andrew@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
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This reverts commit de76e70bc5905fc4ebc8a2e323e16620fa6832ec.
(cherry picked from commit e1e0503d969c8f4bb68a3beedebca5d9238192fd)
Co-authored-by: Jack Koenig <koenig@sifive.com>
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- Remove line defeating having wire locators
`implicit val noSourceInfo = UnlocatableSourceInfo` from `WireDefault#apply`
- Add test to show locators
(cherry picked from commit f701a9f8151891e3bf9019cd3229cb3f2cd1833b)
Co-authored-by: Chick Markley <chick.markley@sifive.com>
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We need to ensure that contextual names stay contextual (ie. sensitive
to the module context which is important for naming ports).
(cherry picked from commit cee255216c4a1bb658a2d8ddc03d966ce7ffb877)
Co-authored-by: Jack Koenig <koenig@sifive.com>
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* Bugfix - OpaqueSlot replace invalid localName (#2701)
(cherry picked from commit fb8ea2a2fac227f2570da992d7877de2eb1cf801)
* Fix cloneTypes (#2703)
Co-authored-by: Aditya Naik <91489422+adkian-sifive@users.noreply.github.com>
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(cherry picked from commit 67cff8253740f19642006dba7eff58b1e5fa1291)
Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
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* Add OpaqueType support to Records (#2662)
OpaqueTypes are essentially type aliases that hide the underlying type.
They are implemented in Chisel as Records of a single, unnamed element
where the wrapping Record does not exist in the emitted FIRRTL.
Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit df5afee2d41b5bcd82d4013b977965c0dfe046fd)
* Fix test compilation
* Fix OpaqueType tests in RecordSpec
Need to implement cloneType correctly and to warn instead of error when
accessing .toTarget of non-hardware types because that is a warning (not
error) in 3.5.
* Waive MiMa false positives
Co-authored-by: Aditya Naik <91489422+adkian-sifive@users.noreply.github.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
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