summaryrefslogtreecommitdiff
path: root/core/src/main/scala
AgeCommit message (Collapse)Author
2021-12-02Refactor Data.toString (#2197)Aditya Naik
Provides a more intuitive implementation of toString for Data. Utilizes the fact that the compiler plugin provides names earlier than Chisel had in the past so we can accurately guess the name of signals even in the currently elaborating module. Co-authored-by: Megan Wachs <megan@sifive.com> Co-authored-by: Jack Koenig <jack.koenig3@gmail.com>
2021-12-01Require the chisel3 compiler plugin (#2271)Jack Koenig
As the chisel3 compiler plugin is now required, we can delete unused code for reflective autoclonetype as well as the noPluginTests.
2021-12-01Bugfix - definition name index skipping with D/I (#2249)Aditya Naik
* Bugfix - definition name index skipping with D/I * Add tests to DefinitionSpec * Add failing test * Fix failing test * Update core/src/main/scala/chisel3/internal/Builder.scala Co-authored-by: Jack Koenig <jack.koenig3@gmail.com> * whitespace * revert package private val Co-authored-by: Jack Koenig <jack.koenig3@gmail.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-11-14remove_toBoolsJiuyang Liu
2021-10-29Exposing more APIs from D/I internals (#2220)Adam Izraelevitz
Exposing more internals of D/I, which are required for supporting D/I with more powerful Chisel libraries: - Exposing IsClone[_] - Exposing InstantiableClone[_] - Gated builders for Instance/Definition - Unsealing Lookupable, with protected accessors for proto and cloned
2021-10-27Add Select APIs for Hierarchy package (#2210)Adam Izraelevitz
* Add Hierarchy trait * Add Hierarchy trait * Add Hierarchy scaladoc * Add license * Add isA and tests * Add back isA * Add new Select APIs for hierarchy package * Update scaladoc * Write outlines for tests * Add tests and fixes to new Select functions * Make calculate via lazy val * Apply suggestions from code review Co-authored-by: Megan Wachs <megan@sifive.com> * Apply suggestions from code review Co-authored-by: Megan Wachs <megan@sifive.com> * Clean up scaladoc * Add shouldNot compile * Apply suggestions from code review Co-authored-by: Megan Wachs <megan@sifive.com> * Bugfix all funcs should analyze root too * Add mdoc, bugfix toDefinition * Make func private, add scaladoc * Update src/test/scala/chiselTests/experimental/hierarchy/InstanceSpec.scala Co-authored-by: Jack Koenig <koenig@sifive.com> * Made protected vals private * Apply suggestions from code review Co-authored-by: Jack Koenig <koenig@sifive.com> * Address code review comments * Added additional null check Co-authored-by: Megan Wachs <megan@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-10-27Add java reflection to hierarchy (#2209)Adam Izraelevitz
* Add Hierarchy trait * Add Hierarchy trait * Add Hierarchy scaladoc * Add license * Add isA and tests * Add back isA * Make calculate via lazy val * Apply suggestions from code review Co-authored-by: Megan Wachs <megan@sifive.com> * Add shouldNot compile * Update src/test/scala/chiselTests/experimental/hierarchy/InstanceSpec.scala Co-authored-by: Jack Koenig <koenig@sifive.com> * Made protected vals private Co-authored-by: Megan Wachs <megan@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-10-25Bugfix: fix isACloneOf (#2205)Adam Izraelevitz
2021-10-25Add Hierarchy trait (#2204)Adam Izraelevitz
2021-10-20Update computeName and callsites (#2192)Aditya Naik
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-10-07Fixed bug with unary minus on FixedPoint and Interval (#2154)Chick Markley
In `Bits.scala`, `FixedPoint` and `Interval` did not defeine the `do_unary_-` methods (the `do_`) was missing The recent PR #2124 combined with the above fact made DspTools break. This fix is necessary to get that repo to build.
2021-10-05Circular-shift (rotate) operations for UInt (#1140)Kamyar Mohajerani
* change static shift behavior to mod width when width is known * add dynamic shift * basic tests that actually do something * MatchedRotateLeftAndRight based on the idea from @chick * BasicRotate rotate "b001" and compare with known values * Fix check for KnownWidth(0|1) as suggested by @aswaterman * Add dontTouch to UIntOps.io (other tests were also optimized out) Co-authored-by: Chick Markley <chick@qrhino.com> Co-authored-by: Andrew Waterman <andrew@sifive.com>
2021-10-05Fix naming of unwrapped val io in Chisel.Modules (#2150)Jack Koenig
The removal of virtual method io accidentally made the naming of io in compatibility mode Bundles sensitive to the prefix at the time of the first access of the field. It also made .suggestName able to override the name. This commit fixes that issue by forcing the name of the io Data to be "io" no matter what.
2021-10-05Deprecate auto-application of empty argument lists to parameterless ↵Jared Barocsi
functions (#2124) * Migrate nullary funcs to parameterless versions * Make deprecation message and dummy arguments clear and consistent Co-authored-by: Megan Wachs <megan@sifive.com>
2021-10-05Remove all Bundle cloneTypes and chiselRuntimeDeprecate its use (#2052)Megan Wachs
* Remove all manual cloneTypes and make it chisel runtime deprecated to add one * runtime deprecate cloneType with runtime reflection * [Backport this commit] Bundle: add check that override def cloneType still works (will be made an error later) * Plugin: make it an error to override cloneType and add a test for that * Docs: can't compile the cloneType anymore * BundleSpec: comment out failing test I cannot get to fail or ignore Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-10-05Remove v3.4.0 version of autoNameRecursively (#2149)Jack Koenig
2021-09-23make all verification statements publically available (#2089)Kevin Laeufer
2021-09-21implement trace API. (#2077)Jiuyang Liu
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-09-08Restore return type of BaseModule.toTarget to ModuleTarget (#2117)Jack Koenig
Definition/Instance introduced the need for representing the targets of instances as InstanceTargets. This original implementation changed the return type of BaseModule.toTarget to express this need. This is a backwards incompatible change that is actually unnecessary because it is impossible for users to get references to the internal InstanceClone objects, instead only accessing such modules via Instance[_] wrappers and cloned Data. We restored the old API by adding a new internal method "getTarget" which will give the correct targets for InstanceClones while maintaining the API of BaseModule.toTarget.
2021-09-05Add Definition and Instance API (#2045)Adam Izraelevitz
This introduces a new experimental API for module instantiation that disentagles elaborating the definition (or implementation) from instantiation of a given module. This solves Chisel's longstanding reliance on "Deduplication" for generating Verilog with multiple instances of the same module. The new API resides in package chisel3.experimental.hierarchy. Please see the hierarchy ScalaDoc, documentation, and tests for examples of use. Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: Megan Wachs <megan@sifive.com> Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-08-31Fix chisel3 <> for compatibility Bundles (Take 3) (#2093)Jack Koenig
Previous incomplete fixes in #2023 and #2031. The legality of a FIRRTL connection is determined by type and flow. Chisel does not have access to true flow information. Previous fix attempts tried to use ActualDirection as a stand-in for flow, but it is incorrect in many cases. This new approach checks the flows of the lvalue and rvalues in the connect and flips the connection if either the lvalue cannot be a sink or the rvalue cannot be a source.
2021-08-30SyncReadMem: fix bug with read(addr) and add some formal tests (#2092)Kevin Laeufer
2021-08-23Remove chisel3's own firrtl Emitter, use firrtl SerializerJack Koenig
This will be slightly slower as it involves converting from Chisel modules to FIRRTL modules before turning them into Strings. This cost is somewhat mitigated by doing that conversion lazily such that we never materialize the entire firrtl Circuit in memory, only 1 module at a time.
2021-08-23Add multiple dimensions to VecInit fill and iterate (#2065)anniej-sifive
Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-08-18Builder: downgrade "Elaborating design" message to info (#2081)Kevin Laeufer
2021-08-18Revert "remove DefRegInit, change DefReg API with option definition. ↵Jack Koenig
(#1944)" (#2080) This reverts commit ed894c61474c8bc73761a6c360ef9d14505d853b.
2021-08-17remove DefRegInit, change DefReg API with option definition. (#1944)Jiuyang Liu
* remove DefRegInit, change DefReg API with option defination. * add error message * use Option[RegInitIR]. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-08-12Add DataView (#1955)Jack Koenig
DataView is a mechanism for "viewing" Scala objects as a subtype of `Data`. Often, this is useful for viewing one subtype of `Data`, as another. One can think about a DataView as a cross between a customizable cast and an untagged union. A DataView has a Target type `T`, and a View type `V`. DataView requires that an implementation of `DataProduct` is available for Target types. DataProduct is a type class that provides a way to iterate on `Data` children of objects of implementing types. If a DataView is provided for a type T to a type V, then the function .viewAs[V] (of type T => V) is available. The object (of type T) returned by .viewAs is called a "View" and can be used as both an rvalue and an lvalue. Unlike when using an .asTypeOf cast, connecting to a "View" will connect to the associated field or fields of the underlying Target. DataView also enables .viewAsSupertype which is available for viewing Bundles as a parent Bundle type. It is similar to .viewAs but requires a prototype object of the Target type which will be cloned in order to create the returned View. .viewAsSupertype maps between the corresponding fields of the parent and child Bundle types.
2021-08-04Added VecInit factory methods (fill,iterate) (#2059)anniej-sifive
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-07-28Bundles can no longer be instantiated with bound hardware (#2046)Jared Barocsi
Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-07-14Fix Cat rename signal (#2011)Leway Colin
Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-07-09Fix chisel3 <> for Bundles that contain compatibility Bundles (Take 2) (#2031)Jack Koenig
PR #2023 fixed a composition issue for chisel3 biconnects delegating to FIRRTL partial connect when compatibility mode Bundles are elements of chisel3 Bundles. It missed an important case though that caused previously working code to break. The bug is fixed by doing the automatic flipping for compatibility mode Bundles that have "Input" as a direction in addition to those that are "Flipped".
2021-07-08Make it legal for concrete resets to drive abstract reset (#2018)Jack Koenig
This has been legal in FIRRTL since v1.2.3 (when reset inference started using a unification-style algorithm) but was never exposed in the Chisel API. Also delete the overridden connects in AsyncReset and ResetType which just duplicate logic from MonoConnect.
2021-07-08Fix chisel3 <> for Bundles that contain compatibility Bundles (#2023)Jack Koenig
BiConnect in chisel3 delegates to FIRRTL <- semantics whenever it hits a Bundle defined in `import Chisel._`. Because chisel3 <> is commutative it needs to be mindful of flippedness when emitting a FIRRTL <- (which is *not* commutative).
2021-07-08Add `isOneOf` method to `ChiselEnum` (#1966)Verneri Hirvonen
* Add @ekiwi's code as a starting point * Add test for ChiselEnum isOneOf method * Make isOneOfTester naming consistent with other testers * Add scaladoc comments for isOneOf * Add isOneOf tests that use the method that takes variable number of args * Add guide level documentation example for isOneOf
2021-07-08Update docs on dontTouch as optimization barrier (#2015)Schuyler Eldridge
Change the Scaladoc for the dontTouch utility. Indicate that this is an _optimization barrier_ and not just a guarantee that the signal won't be removed. The optimization barrier interpretation is the current implementation in the Scala FIRRTL Compiler. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-07-06Make printf return BaseSim subclass so it can be named/annotated (#1992)Deborah Soung
2021-07-01Add ChiselEnum.safe factory method and avoid warningJack Koenig
Previously, ChiselEnum would warn any time a UInt is converted to an Enum. There was no way to suppress this warning. Now there is a factory method (`.safe`) that does not warn and returns (Enum, Bool) where the Bool is the result of calling .isValid on an Enum object. The regular UInt cast is also now smarter and will not warn if all bitvectors of the width of the Enum are legal states.
2021-07-01Change Chisel warnings to use logger instead of printlnJack Koenig
It also uses the same logger as the Builder so that if we ever refactor that to be passed as an argument, it will be the same logger for both Builder and warning reporting.
2021-06-29Change behavior of aop.Select to not include CloneModuleAsRecordJack Koenig
Previously, CloneModuleAsRecord clones would result in the same BaseModule object coming up multiple times when using APIs like .instances, .collectDeep, and .getDeep. This was not the intended behavior and can lead to very subtle bugs.
2021-06-29Restore aop.Select behavior for CloneModuleAsRecordJack Koenig
2021-06-29deprecate getPorts with modulePorts. (#1945)Jiuyang Liu
* deprecate getPorts with modulePorts. * add doc to fullModulePorts and update deprecation notes. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-06-28Set refs for ModuleClone and ClonePorts in less hacky wayJack Koenig
2021-06-28Fix CloneModuleAsRecord support for .toTargetJack Koenig
2021-06-25Correct typos in core/src/main/scala/chisel3/Num.scala (#1976)Felix Yan
2021-06-24create and extend annotatable BaseSim class for verification nodes (#1968)Deborah Soung
* prototype annotating verif constructs * switch to final class * name emissions * moving BaseSim to experimental * adding name tests * fixing quotation escapes * emitting names, but everything has a default name * only name things with provided/suggested names * name every BaseSim node * removing msg, unused imports * fixing file exist calls
2021-04-29Scala 2.13 support (#1751)Jack Koenig
2021-04-29verification: guard statements with module reset (#1891)Kevin Laeufer
2021-04-27Introduce VecLiterals (#1834)Chick Markley
This PR provides for support for Vec literals. They can be one of two forms Inferred: ``` Vec.Lit(0x1.U, 0x2.U) ``` or explicit: ``` Vec(2, UInt(4.W)).Lit(0 -> 0x1.U, 1 -> 0x2.U) ``` - Explicit form allows for partial, or sparse, literals. - Vec literals can be used as Register initializers - Arbitrary nesting (consistent with type constraints is allowed)
2021-04-26Add some error context to Converter .getRefs (#1878)Jack Koenig
generated by cgit v1.2.3 (git 2.25.1) at 2026-01-31 15:03:28 +0000