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2016-08-16Add component to signature.Jim Lawson
2016-08-16Provide public SignalID trait to be used to conjure up a signal identifier.Jim Lawson
2016-08-16Merge branch 'master' into sdtwigg_connectwrap_renamechisel3Jim Lawson
2016-08-15Make "def width" a private API; expose isWidthKnown instead (#257)Andrew Waterman
* Make "def width" a private API; expose isWidthKnown instead Resolves #256. Since width was used to determine whether getWidth would succeed, I added def isWidthKnown: Boolean but another option would be to expose something like def widthOption: Option[Int] ...thoughts? * Document getWidth/isWidthKnown * Add widthOption for more idiomatic Scala manipulation of widths
2016-08-12Use compileOptions to determine if Missing...FieldExceptions are thrown.Jim Lawson
2016-08-12Merge branch 'compile_options' into sdtwigg_connectwrap_renamechisel3Jim Lawson
2016-08-12Add support for per-Module compilation options.Jim Lawson
Nothing uses these now, but when we integrate Stephen's PR200, we'll need a way to selectively enable some strict connection checks on a file by file basis. We plan to do this using package imports which will define suitable compilation options.
2016-08-11Merge branch 'master' into sdtwigg_connectwrap_renamechisel3Jim Lawson
2016-08-09Support Module name overrides with "override def desiredName"Andrew Waterman
The API allowed this before, but not safely, as users could create name conflicts. This exposes the pre-deduplication/sanitization naming API, and closes the other one.
2016-08-09Legalize identifier names before printingAndrew Waterman
It's not entirely clear what the FIRRTL implementation supports, so I'm using the ANSI C requirements for the time being.
2016-08-04Deal with directions on Clocks.Jim Lawson
2016-08-03Merge branch 'master' into sdtwigg_connectwrap_renamechisel3Jim Lawson
2016-07-31Expose asUInt from DataAndrew Waterman
Deprecating toBits removes the capability to cast an arbitrary type to UInt. While it's still possible to do so using asBits.asUInt, this creates boilerplate. (asBits is almost never useful itself.)
2016-07-31Fix two deprecation warningsAndrew Waterman
2016-07-28Add missing factory constructors.Jim Lawson
2016-07-27Additional compatibility code.Jim Lawson
2016-07-25Enable current (chisel2-style) compatibility mode.Jim Lawson
2016-07-25Minimize differences with master.Jim Lawson
Remove .Lit(x) usage. Undo "private" scope change. Change "firing" back to "fire". Add package level NODIR definition.
2016-07-25Merge branch 'master' into sdtwigg_connectwrap_renamechisel3Jim Lawson
2016-07-21Introduce chiselCloneType to distinguish from cloneType.Jim Lawson
Still fails one test - DirectionSpec in Direction.scala
2016-07-20More literal/width rangling.Jim Lawson
2016-07-20Distinguish between ?Int.Lit and ?Int.widthJim Lawson
2016-07-20Generate better names for nodes (#190)Jack Koenig
For Chisel nodes defined in Module class-level values of type Option or Iterable, we can still use reflection to assign names based on the name of the value. This works for arbitrary nesting of Option and Iterable so long as the innermost type is HasId. Note that this excludes Maps which always have an innermost type of Tuple2[_,_].
2016-07-20Compile ok.Jim Lawson
Need to convert UInt(x) into UInt.Lit(x) or UInt.width(x)
2016-07-19Fixes for only connectwrap version.Jim Lawson
2016-07-19Merge in "complete" versions of Mem, Reg.Jim Lawson
2016-07-19Fix LitBinding and MultiAssign tests.Jim Lawson
2016-07-19Remove explicit literal binding.Jim Lawson
2016-07-19Incorporate connection logic.Jim Lawson
Compiles but fails tests.
2016-07-19Merge branch 'sdtwigg_rebase_renamechisel3' into sdtwigg_wrap_renamechisel3Jim Lawson
2016-07-18Update Chisel -> chisel3 references.Jim Lawson
2016-07-18Rename "Chisel" to "chisel3" (only git mv).Jim Lawson
2016-07-15Improve PopCount implementationAndrew Waterman
Clean up Scala code, and use +& to generate a lot less FIRRTL
2016-07-01Reflectively name Module fields declared in superclassesAndrew Waterman
Closes #229 h/t @sdtwigg @davidbiancolin
2016-06-24Merge branch 'master' into renamechisel3Jim Lawson
2016-06-23Expose FIRRTL stop constructAndrew Waterman
2016-06-22Merge branch 'master' into renamechisel3Jim Lawson
2016-06-21Most of the remaining tests with Module, IO wrapping.Jim Lawson
2016-06-21New Module, IO, Input/Output wrapping.Jim Lawson
2016-06-20fix BlackBox setRefs to correctly handle arbitrarily nested bundles as ports ↵Howard Mao
(#223)
2016-06-20Rename "package", "import", and explicit references to "chisel3".Jim Lawson
2016-06-20Rename chisel3 package.Jim Lawson
2016-06-15Generate better node names when names collide (#221)Andrew Waterman
Rather than using a global counter, memoize the last returned value for colliding names to generate smaller sequence numbers.
2016-06-08Move deprecated debug into compatibilityducky
2016-06-08Package split chisel coreducky
2016-06-08Move chisel/... to chisel/core/..., make chisel/compatibility ↵ducky
package/folder, move more things into utils
2016-06-08Rename packages to lowercase chisel, add compatibility layerducky
2016-06-08For Module instances we haven't named, suggest the Module class nameAndrew Waterman
2016-06-06moved do_asUInt implementation into aggregate, it has been to identical ↵chick
separate implementations in Vec and Bundle
2016-06-06moved macro def for toUInt() int to Data and made do_asUInt (the macro ↵chick
target) there as an abstract method. This left clock without a do_asUInt, that has been implemented as an exception at this time
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