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2019-05-10Fix LFSR regressionAndrew Waterman
2019-05-09Merge pull request #1092 from freechipsproject/lfsr-async-resetSchuyler Eldridge
LFSR/PRNG Asynchronous Safety, Use Vec[Bool] to store internal state
2019-05-09PRNG state UInt->Vec[Bool], make async reset safeSchuyler Eldridge
Changes the internal state of PRNG to use Vec[Bool] instead of UInt. This fixes an @aswaterman identified future problem with asynchronous reset. A register with an asynchronous reset can only be reset to a literal. Previously, an LFSR would store state as a UInt. If it was not parameterized with a seed it should have its least significant bit reset to something to avoid locking up. It's ideal to not reset the full UInt (better test coverage, decreased reset fanout). However, it's difficult to only reset one bit of a UInt. Conversely, it's trivial to reset one bit of a Vec[Bool]. This also moves PRNG/LFSR closer to a canonical representation of their internal state, i.e., it's natural to think of generalizing Vec[Bool] to arbitrary finite fields (Vec[A <: Field]) whereas UInt is tightly coupled to GF2. Minor updates: - Updates/fixes to some scaladoc - Add assertion to period test to make sure LFSR is changing Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-09Fix treatment of Vec of Analog and Vec of Bundle of Analog (#1091)Jack Koenig
* IO(Analog) fixed for RawModule * Add a Analog Port for RawModule test & spec * Fixes around Module instantiation and ports in AnalogPortRawModuleTest * Shorten Comment * Add Data.isSynthesizable to distinguish SampleElementBinding This helps clarify the notion of being bound but not hardware. Data.topBindingOpt is now used to get the *actual* top binding, including across SampleElements (eg. in Analog checking that the top is bound to a Port or a Wire) * Fix pretty printing for Vec * Refactor tests for Vec of Analog, add test for Vec of Bundle of Analog
2019-05-09Merge pull request #1088 from freechipsproject/lfsrSchuyler Eldridge
- Add chisel3.util.random package with Galois and Fibonacci LFSRs - Add maximal period LFSR generation and maximal period taps - Deprecate chisel3.util.LFSR16 in favor of chisel3.util.random.LFSR(16)
2019-05-09Deprecate LFSR16, use FibonacciLFSR internallySchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-09Add Lfsr testsSchuyler Eldridge
Add LFSR tests using LFSR16 testing infrastructure. This also adds tests that are the same as the examples shown for LFSR scaladoc. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-09Add chisel3.util.random lib w/ LFSR generatorSchuyler Eldridge
Builds out PRNG and LFSR type hierarchy. PRNG is the base class of LFSR of which Galois and Fibonacci are concrete implementations. PRNGs contain state (a UInt) and an update (delta) function. They have a compile-time optional seed to set the PRNG state. The seed/state can also be set at run-time. PRNGs can be run-time parameterized based on how many updates they should do per cycle and whether or not to send the seed through step-count state updates before loading it. (h/t @jwright6323) LFSRs are parameterized in a reduction operation (XOR or XNOR). An LFSR that does NOT have a seed will be automatically initialized to a minimally safe state (set/reset one bit) based on their reduction operation. (h/t @aswaterman) Adds Galois and Fibonacci LFSRs that define appropriate update functions. Companion objects provide helpers to automatically generate maximal period variants. Taps are provide for a very large set of widths. The LFSR companion object provides an apply method to generate a Fibonacci LFSR random variable (like the old LFSR16).
2019-05-08Genericize LFSR testing infrastructureSchuyler Eldridge
Make LFSR testing generic to enable it to test other LFSRs. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-05Expand upon ScalaDoc in Driveredwardcwang
2019-05-01Make asTypeOf work for bundles with zero-width fields. (#1079)Paul Rigge
Closes #1075.
2019-04-26Bundle literals implementation (#1057)Richard Lin
2019-04-24Add back Int forms of Mem do_apply methods (#1082)Jack Koenig
This is necessary to support code that imports an implicit conversion from Int to UInt
2019-04-23Change size of memories from Int to BigInt (#1076)Jack Koenig
2019-04-19Fix wrong directionality for Vec(Flipped())Edward Wang
Create Chisel IR Port() in a way that Converter is happy with. Also add more extensive test suite for future-proofing. Close #1063
2019-04-16Fork all sbt run and test tasks (#1000)Schuyler Eldridge
This causes sbt tasks (run, test, etc.) to fork to a separate JVM to avoid running out of metaspace. This issue crops up for developers or users repeatedly running sbt tasks in the same sbt session. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-04-15Avoid silently truncating BigInt to IntAndrew Waterman
- Introduce internal helper `castToInt`, which issues an error when the input BigInt can't be represented as Int. - Use `castToInt` wherever we were using `toInt` in a potentially unsafe way.
2019-04-15Style nitpick (#1068)edwardcwang
2019-04-12Implement connectFromBits in ChiselEnum (#1052)Jack Koenig
This is necessary to use ChiselEnum in aggregates where things are casted using .asTypeOf
2019-04-01Detect bundle aliasing (#1050)Richard Lin
2019-03-29Ignore empty aggregates elements when binding aggregate direction (#946)Jack Koenig
Previously, including an empty aggregate in a Bundle would cause a MixedDirectionAggregateException because it has no elements and thus doesn't have a direction * Add SampleElementBinding for Vec sample elements * Add ActualDirection.Empty for bound empty aggregates
2019-03-28Make core.DontCare private to chisel3 (#1054)Jim Lawson
Force clients to access 'DontCare' through the chisel3 package to ensure it's created as a chisel3 object and not a client object.
2019-03-26Try to eliminate JVM hang due to static initialization deadlock (#1053)Jim Lawson
2019-03-25Allow naming annotation to work outside builder context (#1051)Richard Lin
2019-03-25Check field referential equality in autoclonetype (#1047)Richard Lin
2019-03-23Aggregate coverage - aggregate tests but not publishing (#1040)Jim Lawson
Discover a working combination of aggregate usage to enable coverage of subproject testing but publish a single Jar. Use "scalastyle-test-config.xml" for scalastyle config in tests. Enable "_" in method names and accept method names ending in "_=". Re-sync scalastyle-test-config.xml with scalastyle-config.xml This should finally fix #772.
2019-03-23move doNotDedup to experimental (#1008)Sequencer
2019-03-22Add Record to type hierarchy documentationEdward Wang
2019-03-22Undeprecate isLit (#1048)Jack Koenig
2019-03-22Fix enum annotations (#936)Hasan Genc
* Turned off strong enum annotations because they weren't working with Vec indexes * Add new EnumVecAnnotation for vecs of enums and vecs of bundles with enum fields * Changed Clock's width parameter back to a fixed constant value of 1 * Fixed enum annotations for Vecs of Bundles which contain enum elements * Fixed usage of "when/otherwise" to use consistent style
2019-03-21Remove @chiselName from MixedVec (#1045)Richard Lin
2019-03-21Change == to reference equality (eq) in Data print (#1044)Richard Lin
2019-03-20Replace textual release version with Shields SemVer badge. (#1043)Jim Lawson
* Replace textual release version with Shields SemVer badge. * Provide useful button action for release badge.
2019-03-20Mill support for Chisel3 (#1035)edwardcwang
Co-Authored-By: Jack Koenig <jack.koenig3@gmail.com> Co-Authored-By: Jim Lawson <ucbjrl@berkeley.edu>
2019-03-18Split #974 into two PRs - scalastyle updates (#1037)Jim Lawson
* Update style warnings now that subprojects are aggregated. Use "scalastyle-test-config.xml" for scalastyle config in tests. Enable "_" in method names and accept method names ending in "_=". Re-sync scalastyle-test-config.xml with scalastyle-config.xml * Remove bogus tests that crept in with git add * Add missing import.
2019-03-15Merge pull request #1033 from freechipsproject/popcountAndrew Waterman
Tighten inferred width for PopCount
2019-03-15Merge branch 'master' into popcountedwardcwang
2019-03-15Fix typo in linkedwardcwang
2019-03-15Merge branch 'master' into popcountedwardcwang
2019-03-15Use TransitName for improved Pipe naming (#1024)Schuyler Eldridge
This changes from using the chiselname annotation on Pipe.apply to using an explicit TransitName. This results in an improved name for created valid and bits registers. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-03-15Fix PopCount widthAndrew Waterman
2019-03-15Add width constraint to PopCount test (which currently fails)Andrew Waterman
2019-03-15Add PopCount testAndrew Waterman
2019-03-14Decouple implementation details from LoadMemoryAnnotation. (#1034)Jim Lawson
2019-03-13Update recommended verilator version to 4.006 (#1032)Jim Lawson
2019-03-11ScalaDocs improvement for utils Math, MixedVec (#1019)Richard Lin
2019-02-25Docs for ListLookup (#1028)Richard Lin
Co-Authored-By: ducky64 <elpato25@gmail.com> Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@gmail.com> Co-Authored-By: Edward Wang <edward.c.wang@compdigitec.com>
2019-02-20Update templates to include documentation. (#1026)Paul Rigge
2019-02-19Add HasBlackBoxPath to BlackBoxUtils.scala (#903)Albert Chen
* Add HasBlackBoxPath trait * Use 'setResource' instead of 'addResource' * Add ScalaDoc
2019-02-19ScalaDoc for Mux (examples added) (#1014)Martin Schoeberl
Co-Authored-By: schoeberl <martin@jopdesign.com> Co-Authored-By: Edward Wang <edward.c.wang@compdigitec.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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