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AgeCommit message (Expand)Author
2020-12-07(encore) Builder: use LazyLogging.logger.warn to print elaboration message (#...Jiuyang Liu
2020-12-01Fix RegInit of Bundle lits (#1688)Jack Koenig
2020-12-02readme: simplify sbt snippet and update to the latest stable release (#1686)Kevin Laeufer
2020-11-24Update some README links to chipsalliance (#1673)Jack Koenig
2020-11-16Improve source locators for switch statements. (#1669)Daniel Kasza
2020-11-11Add custom mdoc modifier for emitted Verilog (#1666)Jack Koenig
2020-11-11Ignore tests using System.setSecurityManager (#1661)Jack Koenig
2020-11-11Refine autonaming to have more intuitive behavior (#1660)Jack Koenig
2020-11-05For HasId.setRef, have first set win (with force override) (#1655)Jack Koenig
2020-11-03Remove Data.setRef assertion (#1654)Jack Koenig
2020-11-02SeqUtils asUInt endian-ness: hi/lo instead of right/left (#1647)John Ingalls
2020-11-02Bugfix - adding external modules was broken (#1649)Adam Izraelevitz
2020-10-30Fix bug where refs may not get set for Records (#1645)Jack Koenig
2020-10-27Fix broken links in docs (#1643)Adam Izraelevitz
2020-10-26Fix crosslinks in mdoc. Can't use md suffix (#1640)Adam Izraelevitz
2020-10-26Bugfix - module name collision for injecting aspect (#1635)Adam Izraelevitz
2020-10-26Added Force Name API (#1634)Adam Izraelevitz
2020-10-26Fixed broken link to type hierarchy diagram (#1611)PENGUINLIONG
2020-10-26Delete index.md (#1613)Adam Izraelevitz
2020-10-22Use Data refs for name prefixing with aggregate elements (#1616)Jack Koenig
2020-10-21Make `-e` option work with ChiselStage methods (#1630)Schuyler Eldridge
2020-10-19Change prefix stack to List[String] (#1617)Jack Koenig
2020-10-19Enable Cat of Zero Element Vec (#1623)Schuyler Eldridge
2020-10-14Provide user source locators in Builder.error errors (#1618)Jack Koenig
2020-10-13ExtModule's lacked support built in support for providing (#1154)Chick Markley
2020-10-12When prefixing with a data, eagly get local name (#1614)Jack Koenig
2020-10-12Update junit to 4.13.1 (#1612)Scala Steward
2020-10-11Add 3.4.x to Mergify (#1607)Jack Koenig
2020-10-05Move more docs (#1601)Adam Izraelevitz
2020-10-01Move Chisel3 to SPDX license conventions (#1604)Chick Markley
2020-09-24Fix broken mdoc (#1600)Adam Izraelevitz
2020-09-22Support using switch without importing SwitchContext (#1595)Jack Koenig
2020-09-15make parameters for util modules public (#1452)Albert Chen
2020-09-15Improve performance of ChiselPlugin (#1590)Jack Koenig
2020-09-14Documentation and minor plugin changes. (#1573)Adam Izraelevitz
2020-09-09Recursively generate one-hot multiplexers for aggregates (#1557)Jerry Zhao
2020-09-09Add new annotation for Chisel Circuit serialization (#1580)Jack Koenig
2020-09-09Fix load memory from file to work with binary (#1583)HappyQuark
2020-09-04Better Building of FIRRTL From Source (#1563)Jack Koenig
2020-09-03Bug fix for build.sc (#1579)Jiuyang Liu
2020-09-02Add chisel plugin to mill build system. (#1572)Jiuyang Liu
2020-08-27Restore and deprecate Chisel.Driver (#1571)Jack Koenig
2020-08-27Update README.md (#1570)Martin Schoeberl
2020-08-26Add ChiselPhase, Stop writing files in ChiselStage$ methods, Expand ChiselSta...Schuyler Eldridge
2020-08-25Relax plugin scalac phase order (#1568)Jack Koenig
2020-08-21Updated PR template to include checklist and documentation updates (#1562)Adam Izraelevitz
2020-08-21Move multi-clock to explanations (#1561)Adam Izraelevitz
2020-08-21Added website docs and mdoc. (#1560)Adam Izraelevitz
2020-08-20Remove use of PreservesAll, cleanup dependencies (#1558)Schuyler Eldridge
2020-08-14fix build release problem (#1556)Chick Markley
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